Power semiconductor device and method therefor

• US 20060226498A1
• Filed: 03/23/2006
• Published: 10/12/2006
• Est. Priority Date: 01/06/2005
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce
• Granted Patent: US 8,530,963 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Claims

1-42. -42. (canceled)

43. A semiconductor device comprising:

a semiconductor die having an active area including a plurality of transistor cells, each cell including a source region, a gate and a drain region;

a gate interconnect coupled to the gates of the cells, said gate interconnect being located adjacent a periphery of the die, wherein the gate interconnect comprises metal; and

a shielding plate between at least a portion of the gate interconnect and the drain region of at least one transistor cell of the plurality of transistor cells to reduce gate to drain capacitance, wherein the shielding plate is coupled to the source region of a first transistor cell of the plurality of transistor cells.

44. The device of claim 43 wherein the gates of the cells are located in a central portion of the die and conductive pathways run from each gate region outwardly to the external gate interconnect, wherein the shielding plate also being is located under the conductive pathways.

45. The device of claim 44 wherein the source and drain regions are formed in an epitaxial layer adjacent an upper surface of the die and the cells share a common drain formed at least in part by a heavily doped region under the epitaxial layer.

46. A semiconductor device comprising:

a semiconductor die comprising a plurality of mesh-connected transistor cells wherein each cell has a source region, a gate and a drain region;

the source regions of the cells are located adjacent a first surface of the die;

the gates of the cells are located adjacent the first surface of the die;

a drain electrode coupled to the drain regions of the cells and adjacent to a second surface of the die, wherein the second surface is opposite the first surface;

a conductive pathway extending radially outwardly from the gates of the cells to provide control signals to the gates of the cells; and

a shielding plate located substantially between the conductive pathway and the drain regions of the cells to reduce gate to drain capacitance, wherein the shielding plate is coupled to the source region of a first transistor cell of the Plurality of mesh-connected transistor cells.

47. The device of claim 46 wherein the gates of the cells are located in a central portion of the die and the conductive pathway run from each gate outwardly to a conductive gate interconnect surrounding at least a portion of the cells, wherein the shielding plate is located under the gate interconnect.

48. The device of claim 47 wherein the source and drain regions are formed in an epitaxial layer adjacent an upper surface of the die and the cells share a common drain formed at least in part by a heavily doped region under the epitaxial layer.

49-138. -138. (canceled)

139. A semiconductor device, comprising:

a semiconductor material;

an active area in the semiconductor material;

a transistor having a gate, a drain region, a source region in the active area, a source electrode coupled to the source region, and a drain electrode;

a first region of a first conductivity type extending from a first surface of the semiconductor material into the semiconductor material, wherein the first region is contiguous around the periphery of the active area; and

a layer of conductive material over the first surface of the semiconductor material and adjacent to a portion of the gate of the transistor to reduce gate to drain capacitance, wherein the layer of conductive material is coupled to the first region and electrically coupled to the source electrode of the transistor.

140. The semiconductor device of claim 139,

further comprising a gate interconnect coupled to the gate;

wherein the layer of conductive material is a layer of polysilicon;

wherein at least a portion of the gate interconnect is over the layer of conductive material to reduce gate to drain capacitance; and

wherein the first region is directly connected to the layer of conductive material at the first surface of the semiconductor material.

141. The semiconductor device of claim 139, wherein the transistor includes a second region of the first conductivity type coupled to the first region and extending from a first surface of the semiconductor material into the semiconductor material, wherein a portion of the second region is a channel region of the transistor, wherein the channel region has a substantially constant doping concentration, and wherein a depth of the first region relative to the first surface of the semiconductor material is approximately equal to a depth of the second region.

142. The semiconductor device of claim 139, wherein the source electrode is adjacent the first surface of the semiconductor material and wherein the drain electrode is adjacent a second surface of the semiconductor material, wherein the second surface is opposite the first surface.

143. The semiconductor device of claim 139, wherein the transistor is a vertical radio frequency (RF) power transistor.

144. A semiconductor device, comprising:

a semiconductor material having a first surface and a second surface opposite the first surface;

a transistor having a drain region in the semiconductor material, a source region in the semiconductor material, a channel region in the semiconductor material, and a gate over the first surface of the semiconductor material, wherein the gate length of the transistor is formed non-photolithographically, wherein the gate comprises an electrically conductive material, and wherein the gate length of the transistor is approximately equal to the deposition thickness of the layer of electrically conductive material;

a drain interconnect coupled to the drain region; and

a source interconnect coupled to the source region and separated from the gate, wherein the gate is a contiguous structure surrounding at least a portion of the source interconnect.

145. The semiconductor device of claim 144, wherein the source interconnect comprises a metal, the gate comprises a layer of polysilicon, and the semiconductor material is an epitaxial layer.

146. The semiconductor device of claim 144, wherein the transistor is a vertical field effect transistor (FET), the gate is adjacent the first surface of the semiconductor material, the source interconnect is adjacent the first surface of the semiconductor material, and the drain interconnect is adjacent the second surface of the semiconductor material.

147. The semiconductor device of claim 144, wherein the gate comprises a first layer of polysilicon and a second layer of polysilicon and wherein the gate length is the combined deposition thickness of the first and second layers of polysilicon.

148. The semiconductor device of claim 144, wherein the source region is of a first conductivity type and wherein the transistor is a vertical transistor that further comprises a doped region of a second conductivity type formed in the channel region, wherein the source interconnect is coupled to the doped region and the source region.

149. A semiconductor device, comprising:

a semiconductor material;

an active area;

a transistor having a gate over a first surface of the semiconductor material, a source region in the active area, a drain region, a source electrode coupled to the source region, and a drain electrode coupled to the drain region;

a first layer of conductive material over the first surface of the semiconductor material and adjacent to a portion of the gate of the transistor to reduce gate to drain capacitance; and

a dielectric structure extending at least about four microns from the first surface of the semiconductor material into the semiconductor material, wherein at least a portion of the first layer of conductive material is over the dielectric structure.

150. The semiconductor device of claim 149,

wherein the first layer of conductive material is a layer of polysilicon;

and

wherein a portion of the first layer of conductive material is substantially between the gate and the drain region to reduce gate to drain capacitance; and

wherein the first layer of conductive material is electrically coupled to the source electrode of the transistor.

151. The semiconductor device of claim 149,

wherein the semiconductor material is an epitaxial layer;

wherein the source region of the transistor and the drain region of the transistor are formed in the epitaxial layer; and

wherein the dielectric structure extends from the first surface through the epitaxial layer and a wall of the dielectric structure adjacent to the outer boundary of the active area provides edge termination to maintain substantially planar equipotential lines in said epitaxial layer during operation of the semiconductor device.

152. The semiconductor device of claim 149,

wherein the dielectric structure comprises an oxide;

wherein the dielectric structure is at least about 10 microns wide; and

wherein the dielectric structure surrounds the active area.

153. The semiconductor device of claim 149, wherein the area of the dielectric structure is approximately equal to at least 10% of the total area of the semiconductor material.

154. The semiconductor device of claim 149, wherein the dielectric structure is a solid structure substantially devoid of any air gaps.

155. The semiconductor device of claim 149, wherein the dielectric structure includes an air gap.

156. The semiconductor device of claim 149, further comprising:

a second layer of conductive material over the first layer of conductive material and adjacent to the portion of the gate of the transistor, wherein at least a portion of the second layer of conductive material is over the dielectric structure; and

a third layer of conductive material over the second layer of conductive material and adjacent to the portion of the gate of the transistor, wherein at least a portion of the third layer of conductive material is over the dielectric structure.

157. The semiconductor device of claim 156, wherein the first layer comprises polysilicon, the second layer comprises a silicide, and the third layer comprises polysilicon.

158. A semiconductor device, comprising:

a semiconductor material;

a first region of a first conductivity type in the semiconductor material;

a second region of a second conductivity type in the semiconductor material adjacent to the first region, wherein the second region has a higher doping concentration than the semiconductor material, wherein the first region and the second region extend from a top surface of the semiconductor material into the semiconductor material, and wherein a depth of the second region relative to the top surface of the semiconductor material is approximately equal to a depth of the first region;

a third region of the second conductivity type extending from the top surface of the semiconductor material into the semiconductor material;

a conductive material over the first region; and

a dielectric structure in the semiconductor material and adjacent to an area that includes the first region, wherein the dielectric structure extends at least about four microns from the top surface of the semiconductor material into the semiconductor material.

159. The semiconductor device of claim 158, wherein the first region is adjacent the top surface of the semiconductor material, the second region is adjacent the top surface of the semiconductor material, and the second region is electrically coupled to the first region.

160. The semiconductor device of claim 158, wherein the semiconductor device comprises a transistor and wherein the transistor comprises:

a portion of the semiconductor material;

the first region, wherein a portion of the first region is a channel region of the transistor;

the second region, wherein the second region and the portion of the semiconductor material are a drain region of the transistor and wherein the second region is adjacent to the first region to reduce the on-resistance (Rdson) of the transistor;

the third region, wherein the third region is a source region of the transistor;

the conductive material, wherein the conductive material is polysilicon and is a gate of the transistor and wherein the conductive material is over the top surface of the semiconductor material; and

a gate interconnect coupled to the gate.

161. The semiconductor device of claim 160, wherein the source region is in the first region, the channel region of the transistor surrounds the source region of the transistor, the channel region has an approximately constant doping concentration, and a channel length of the channel region is approximately equal to the thickness of the conductive material.

162. The semiconductor device of claim 161, wherein the channel length is equal to or less than approximately 0.35 microns (μ

m).

163. The semiconductor device of claim 160, wherein the transistor is a vertical radio frequency (RF) power transistor.

164. The semiconductor device of claim 160, further comprising:

a source electrode coupled to the source region and adjacent to the top surface of the semiconductor material; and

a drain electrode coupled to the drain region and adjacent to a bottom surface of the semiconductor material, wherein the bottom surface is opposite the top surface.

165. The semiconductor device of claim 160, further comprising a layer of conductive material over the top surface of the semiconductor material and adjacent to the gate of the transistor.

166. The semiconductor device of claim 165, wherein the layer of conductive material is a layer of polysilicon and is over the upper surface of the semiconductor material and wherein at least a portion of the gate interconnect is over the layer of conductive material to reduce gate to drain capacitance.

167. The semiconductor device of claim 165, wherein the layer of conductive material is a shield and is electrically coupled to the source region of the transistor.

168. The semiconductor device of claim 165, further comprising a fourth region of the first conductivity type in the semiconductor material, coupled to the first region, and adjacent to the dielectric structure.

169. The semiconductor device of claim 168, wherein the layer of conductive material is coupled to the fourth region and wherein the fourth region extends from a top surface of the semiconductor material into the semiconductor material and wherein a depth of the second region relative to the top surface of the semiconductor material is less than a depth of the fourth region.

170. The semiconductor device of claim 160, wherein the dielectric structure surrounds the source region and is adjacent to the conductive material.

171. The semiconductor device of claim 160, wherein at least a portion of the gate interconnect is over the dielectric structure.

172. The semiconductor device of claim 158, wherein the dielectric structure is at least about ten microns wide.

173. The semiconductor device of claim 158, wherein the dielectric structure comprises an oxide and wherein the dielectric structure is a solid dielectric structure substantially devoid of any air gaps.

174. The semiconductor device of claim 158, wherein the dielectric structure includes an air gap.

175. The semiconductor device of claim 158, wherein the dielectric structure includes a vertical structure adjacent to the transistor to stand off a voltage of approximately 75 volts.

176. The semiconductor device of claim 158,

wherein the semiconductor material includes a semiconductor substrate and an epitaxial layer over the semiconductor substrate;

wherein the first region, the second region, and the third region are formed in the epitaxial layer;

wherein the dielectric structure extends from the first surface of the epitaxial layer through the epitaxial layer;

wherein the dielectric structure is a ring structure that surrounds the first region; and

wherein the area of the dielectric structure is approximately equal to at least 10% of the total area of the semiconductor material.

177. The semiconductor device of claim 158, wherein the semiconductor material is an epitaxial layer of the second conductivity type.

178. A semiconductor device, comprising:

a semiconductor material;

an active area in the semiconductor material;

a first region of a first conductivity type in the active area extending from a first surface of the semiconductor material into the semiconductor material;

a second region of a second conductivity type in the active area extending from the first surface of the semiconductor material into the semiconductor material;

a third region of the second conductivity type in the active area extending from the first surface of the semiconductor material into the semiconductor material;

a fourth region of the first conductivity type in the active area extending from the first surface of the semiconductor material into the semiconductor material; and

a dielectric structure extending at least about four microns from a surface of the semiconductor material into the semiconductor material, wherein the dielectric structure is a structure surrounding the active area and wherein the fourth region is contiguous around the periphery of the active area and adjacent to the dielectric structure.

179. The semiconductor device of claim 178, wherein the active area includes a transistor and wherein the transistor comprises:

the first region abutting the fourth region, wherein a portion of the first region is a channel region of the transistor and wherein a depth of the fourth region relative to the first surface of the semiconductor material is greater than a depth of the first region;

the second region of a second conductivity type coupled to the first region, wherein the second region is a portion of the drain region of the transistor;

the third region of the second conductivity type coupled to the first region, wherein the third region is a source region of the transistor; and

an electrically conductive material, wherein the electrically conductive material is polysilicon and is a portion of a gate of the transistor and wherein the electrically conductive material is over the first surface of the semiconductor material and over the first region.

180. The semiconductor device of claim 179, wherein the transistor is a vertical transistor.

181. The semiconductor device of claim 179,

wherein the semiconductor material includes an epitaxial layer extending from a first surface of the semiconductor material into the semiconductor material;

wherein the fourth region, the first region, the second region, and the third region are formed in the epitaxial layer;

wherein the area of the dielectric structure is approximately equal to at least 10% of the total area of the semiconductor substrate; and

wherein the dielectric structure extends from the first surface through the epitaxial layer and a wall of the dielectric structure adjacent to the outer boundary of the active area provides edge termination to maintain substantially planar equipotential lines in the epitaxial layer during operation of the semiconductor device.

182. The semiconductor device of claim 179, further comprising a layer of conductive material over the first surface of the semiconductor material and adjacent to a portion of the gate of the transistor to reduce gate to drain capacitance.

183. The semiconductor device of claim 182,

wherein the layer of conductive material is a layer of polysilicon;

wherein at least a portion of the gate is over the layer of conductive material to reduce gate to drain capacitance; and

wherein the fourth region is electrically coupled to the source region of the transistor; and

wherein the fourth region is directly connected to the layer of conductive material at the first surface of the semiconductor material.

184. The semiconductor device of claim 178, wherein the dielectric structure is a ring structure surrounding the active area and wherein the fourth region is a ring shaped region coupled to the dielectric structure.

185. A semiconductor device, comprising:

a semiconductor material;

a vertical transistor having a gate, a drain region, a source region, and a channel region, wherein the channel region of the vertical transistor is in the semiconductor material and has a substantially constant doping concentration; and

a dielectric structure extending from a first surface of the semiconductor material into the semiconductor material at least about 4 microns.

186. The semiconductor device of claim 185, wherein vertical transistor is a radio frequency (RF) transistor constructed to operate at frequencies of greater than about 500 MHz.

187. The semiconductor device of claim 185,

wherein a portion of the gate of the vertical transistor is over the dielectric structure to reduce gate to drain capacitance;

wherein the semiconductor material is an epitaxial layer;

wherein the source region of the transistor and the drain region of the transistor are formed in the epitaxial layer; and

wherein the dielectric structure extends from the first surface of the epitxial layer through the epitaxial layer.

188. The semiconductor device of claim 185,

wherein the dielectric structure comprises an oxide;

and

wherein the dielectric structure surrounds the vertical transistor.

189. The semiconductor device of claim 185, wherein the area of the dielectric structure is approximately equal to at least 10% of the total area of the semiconductor material.

190. The semiconductor device of claim 185, wherein the dielectric structure is a solid structure substantially devoid of any air gaps.

191. The semiconductor device of claim 185, wherein the dielectric structure includes an air gap.

192. The semiconductor device of claim 185, further comprising a layer of conductive material over the first surface of the semiconductor material, wherein at least a portion of the gate is over the layer of conductive material to reduce gate to drain capacitance and wherein the layer of conductive material is electrically coupled to the source region of the vertical transistor.