Semiconductor device incorporating protective diode with stable ESD protection capabilities

• US 20060226499A1
• Filed: 03/30/2006
• Published: 10/12/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: RICOH Electronic Devices Co., Ltd. (Nisshinbo Holdings Incorporated)
• Original Assignee: Ricoh Company Limited
• Inventors: Shimizu, Akira
• Granted Patent: US 7,420,255 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7818 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A semiconductor device provided with stable ESD protection capabilities, incorporating a transistor and a protective diode to form a power control IC. The semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, formed in the semiconductor substrate; the transistor formed in the well region; a guard ring region of the second conductivity type having an impurity concentration higher than the well region, formed on the surface of the semiconductor substrate inside the periphery of, and spatially separated from the boundary of, the well region; a substrate pickup region of the first conductivity type having an impurity concentration higher than the semiconductor substrate, formed on the periphery of the well region in contact with the well region and the semiconductor substrate; and a thick oxide film formed on the surface of the semiconductor substrate between the guard ring region and the substrate pickup region. The protective diode is formed including the well region, the guard ring region, and the substrate pickup region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type opposite to the first conductivity type, formed in said semiconductor substrate;

a transistor formed in said well region;

a guard ring region of the second conductivity type having an impurity concentration higher than said well region, formed on a surface of said semiconductor substrate inside a periphery, and spatially separated from a boundary, of said well region;

a substrate pickup region of the first conductivity type having an impurity concentration higher than said semiconductor substrate, formed on the periphery of said well region in contact with said well region and said semiconductor substrate;

a thick oxide film formed on the surface of said semiconductor substrate between said guard ring region and said substrate pickup region; and

a protective diode formed of said well region, said guard ring region, and said substrate pickup region.

2. The semiconductor device according to claim 1, wherein said substrate pickup region is formed of a first double-diffusion layer including:

a low concentration diffusion layer of the first conductivity type having an impurity concentration higher than said semiconductor substrate, formed in a self-aligned manner using said thick oxide film as a mask, and

a high concentration diffusion layer of the first conductivity type having another impurity concentration higher than said low concentration diffusion layer.

3. The semiconductor device according to claim 2, wherein said transistor is an LDMOS transistor, said LDMOS transistor comprising:

a channel diffusion layer of the first conductivity type, formed in said well region, said well region serving as a drain; and

a source of the second conductivity type, formed in said channel diffusion layer, a portion of said channel diffusion layer on the surface of said semiconductor substrate immediately under a gate electrode serving as a channel region, and wherein

said channel region is formed simultaneously with said low concentration diffusion layer.

4. The semiconductor device according to claim 2, wherein said transistor is an LDMOS transistor, said LDMOS transistor comprising:

a channel diffusion layer of the first conductivity type, formed in said well region, said well region serving as a drain; and

a source of the second conductivity type, formed in said channel diffusion layer, a portion of said channel diffusion layer on the surface of said semiconductor substrate immediately under a gate electrode serving as a channel region, and wherein

said LDMOS transistor further comprises a drain contact diffusion layer of the second conductivity type, formed in said well region, said drain contact diffusion layer being formed contiguously to said guard ring region.

5. The semiconductor device according to claim 4, wherein said guard ring region is formed of a second double-diffusion layer, said second double-diffusion layer being formed in a self-aligned manner using said thick oxide film as a mask, including:

a low concentration diffusion layer of the second conductivity type having an impurity concentration higher than said well region, and

a high concentration diffusion layer of the second conductivity type having another impurity concentration higher than said low concentration diffusion layer.

6. The semiconductor device according to claim 5, wherein said protective diode is formed to have a rated voltage higher than a nominal rated voltage and a breakdown voltage lower than that of said transistor.

7. The semiconductor device according to claim 6, wherein said guard ring region and said substrate pickup region are formed spatially separated from each other.

8. The semiconductor device according to claim 7, wherein said transistor is provided with another thick oxide film formed simultaneously with said thick oxide film such that a gate electrode is formed to extend covering at least a portion of said another thick oxide film.

9. The semiconductor device according to claim 8, wherein said another thick oxide film is a LOCOS oxide film.

10. The semiconductor device according to claim 8, wherein said another thick oxide film is formed without being embedded into said semiconductor substrate, having a cross section approximately of a trapezoidal shape when viewed from thickness direction.

11. The semiconductor device according to claim 8, wherein said well region is electrically connected to a source terminal of an apparatus configured to supply a source voltage to a peripheral circuit.

12. The semiconductor device according to claim 1, wherein said protective diode is formed to have a rated voltage higher than a nominal rated voltage and a breakdown voltage lower than that of said transistor.

13. The semiconductor device according to claim 1, wherein said guard ring region and said substrate pickup region are formed spatially separated from each other.

14. The semiconductor device according to claim 1, wherein said transistor is provided with another thick oxide film formed simultaneously with said thick oxide film such that a gate electrode is formed to extend covering at least a portion of said another thick oxide film.

15. The semiconductor device according to claim 1, wherein said well region is electrically connected to a source terminal of an apparatus configured to supply a source voltage to a peripheral circuit.

16. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type opposite to the first conductivity type, formed in said semiconductor substrate;

a transistor formed in said well region;

a guard ring region of the second conductivity type having an impurity concentration higher than said well region, formed on a periphery of said well region in contact with said well region and said semiconductor substrate;

a substrate pickup region of the first conductivity type having an impurity concentration higher than said semiconductor substrate, formed on a surface of said semiconductor substrate outside the periphery of, and spatially separated from said well region;

a thick oxide film formed between said guard ring region and said substrate pickup region on the surface of said semiconductor substrate; and

a protective diode formed of said well region, said guard ring region, and said substrate pickup region.

17. The semiconductor device according to claim 16, wherein said guard ring region is formed of a first double-diffusion layer, said first double-diffusion layer being formed, in a self-aligned manner using said thick oxide film as a mask, including:

a low concentration diffusion layer of the second conductivity type having an impurity concentration higher than said well region, and

a high concentration diffusion layer of the second conductivity type having another impurity concentration higher than said low concentration diffusion layer.

18. The semiconductor device according to claim 17, wherein said transistor is an LDMOS transistor, said LDMOS transistor comprising:

a channel diffusion layer of the second conductivity type, formed in said well region, a portion of said channel diffusion layer on the surface of said semiconductor substrate immediately under a gate electrode serving as a channel region;

a low impurity concentration drain of the first conductivity type, formed in said well region on the surface of said semiconductor substrate in contact with said channel diffusion layer;

a source of the first conductivity type, formed in said channel diffusion layer; and

a drain contact diffusion layer of the first conductivity type, formed in said low impurity concentration drain, and wherein

said channel region is formed simultaneously with said guard ring region.

19. The semiconductor device according to claim 18, wherein said substrate pickup region is formed of a second double-diffusion layer, said second double-diffusion layer being formed in a self-aligned manner using said thick oxide film as a mask, including:

a low concentration diffusion layer of the first conductivity type having an impurity concentration higher than said semiconductor substrate, and

a high concentration diffusion layer of the first conductivity type having another impurity concentration higher than said low concentration diffusion layer.

20. The semiconductor device according to claim 19, wherein said protective diode is formed to have a rated voltage higher than a nominal rated voltage and a breakdown voltage lower than that of said transistor.

21. The semiconductor device according to claim 20, wherein said guard ring region and said substrate pickup region are formed spatially separated from each other.

22. The semiconductor device according to claim 21, wherein said transistor is provided with another thick oxide film formed simultaneously with said thick oxide film such that a gate electrode is formed to extend covering at least a portion of said another thick oxide film.

23. The semiconductor device according to claim 22, wherein said another thick oxide film is a LOCOS oxide film.

24. The semiconductor device according to claim 22, wherein said another thick oxide film is formed without being embedded into said semiconductor substrate, having a cross section approximately of a trapezoidal shape when viewed from thickness direction.

25. The semiconductor device according to claim 22, wherein said well region is electrically connected to a source terminal of an apparatus configured to supply a source voltage to a peripheral circuit.

26. The semiconductor device according to claim 16, wherein said protective diode is formed to have a rated voltage higher than a nominal rated voltage and a breakdown voltage lower than that of said transistor.

27. The semiconductor device according to claim 16, wherein said guard ring region and said substrate pickup region are formed spatially separated from each other.

28. The semiconductor device according to claim 16, wherein said transistor is provided with another thick oxide film formed simultaneously with said thick oxide film such that a gate electrode is formed to extend covering at least a portion of said another thick oxide film.

29. The semiconductor device according to claim 16, wherein said well region is electrically connected to a source terminal of an apparatus configured to supply a source voltage to a peripheral circuit.