NITRIDATION OF STI LINER OXIDE FOR MODULATING INVERSE WIDTH EFFECTS IN SEMICONDUCTOR DEVICES

• US 20060226559A1
• Filed: 04/11/2005
• Published: 10/12/2006
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Niimi, Hiroaki, Mehrotra, Manoj
• Granted Patent: US 7,199,020 B2
• Time in Patent Office: Days
• US Class Current: 438/425
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

Claims

1. A method of fabricating a semiconductor device containing isolation structures, the method comprising:

defining isolation regions and active regions of a semiconductor body;

forming trench regions within the isolation regions of the semiconductor body;

nitriding surfaces of the trench regions;

oxidizing the nitrided surfaces of the trench regions to form nitrogen containing liners; and

filling the trench regions with a dielectric fill material.

2. The method of claim 1, wherein forming trench regions within isolation regions comprises forming a resist mask that exposes the isolation regions and etching the exposed regions for a selected time to form the trench regions with a bottom and sidewalls.

3. The method of claim 1, wherein forming trench regions within isolation regions comprises forming a hard mask that exposes the isolation regions and etching the exposed regions to form the trench regions with a bottom and sidewalls.

4. The method of claim 3, wherein the hard mask is comprised of silicon nitride.

5. The method of claim 1, wherein nitriding surfaces of the trench regions comprises performing a plasma based nitridation process.

6. The method of claim 2, wherein the plasma nitridation process Is performed for a duration selected to obtain a desired nitrogen concentration at liner/substrate interfaces.

10. The method of claim 1, further comprising performing an anneal after forming the nitrogen containing liners.

11. The method of claim 1, wherein filling the trench regions comprises depositing oxide over the device.

12. The method of claim 1, wherein filling the trench regions comprises:

forming a hard mask layer prior to forming the trench regions;

depositing an oxide material in the trench regions using a high density plasma deposition process; and

planarizing the device using the hard mask as a planarization stop.

13. The method of claim 12, wherein planarizing the device comprises performing a chemical mechanical polish of the oxide material.

14. The method of claim 1, further comprising forming transistor devices within the active regions of the semiconductor body.

7. (canceled)

8. The method of claim 7, wherein the thermal growth process is performed for a duration selected according to a desired thickness for the nitrogen containing liners.

9. (canceled)

15. (canceled)

16. A method of fabricating a semiconductor device containing isolation structures, the method comprising:

forming a pad oxide layer over a semiconductor body;

forming a hard mask layer on the pad oxide layer;

forming a resist mask on the hard mask layer that exposes the hard mask layer within isolation regions and covers the hard mask layer within active regions of the device;

patterning the hard mask layer to expose the semiconductor body within isolation regions;

performing an etch process using the hard mask layer as a mask that forms trench regions within the isolation regions;

nitriding exposed surfaces of the trench regions;

oxidizing the exposed surfaces of the trench regions to form nitrogen containing liners; and

filling the trench regions with a dielectric fill material.

17. The method of claim 16, further comprising removing the resist layer prior to performing the etch process that forms trench regions.

18. The method of claim 16, further comprising removing the hard mask layer after filling the trench regions with the dielectric fill material.

19. A method of fabricating a semiconductor device containing isolation structures, the method comprising:

defining an isolation region of the semiconductor device;

performing an etch process using a mask that forms a trench region within the isolation region, wherein the trench region comprises a bottom surface and sidewall surfaces;

nitriding the bottom surface and the sidewall surfaces of the trench region;

oxidizing the nitrided bottom surface and the sidewall surfaces of the trench regions to form a nitrogen containing liner;

repairing damage incurred during the oxidizing with an anneal; and

filling the trench region with a dielectric fill material.

20. The method of claim 19, wherein the anneal is performed for a duration selected according to a thickness of the nitrogen containing liner.