Method of increasing reliability of packaged semiconductor integrated circuit dice

• US 20060226862A1
• Filed: 06/13/2006
• Published: 10/12/2006
• Est. Priority Date: 09/14/2004
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Suciu, Paul I., Marcus, Kristopher R., Friedberg, Charles B.
• Granted Patent: US 7,452,733 B2
• Time in Patent Office: Days
• US Class Current: 438/15
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding the core die and at least one additional die from the die cluster to a weighted character map, and assigning a weighting value to each of the dice added to the weighted character map. At least one tier of buffer dice is then added to the weighted character map adjacent to each die on the weighted character map. Both the dice from the die cluster and the tier of buffer dice are marked, thereby preventing those dice from being packaged and consequently, shipped to customers.

Claims

1. A method to increase a reliability of packaged semiconductor integrated circuit dice, the method comprising:

identifying one or more dice having failed an electrical test;

adding the one or more failed dice to a weighted character map;

adding a first tier of buffer dice to the weighted character map adjacent to each die on the weighted character map; and

indicating both the failed dice and the tier of buffer dice, thereby indicating dice not requiring packaging.

2. The method of claim 1 wherein the step of adding one or more dice having failed an electrical test are added to a weighted character map further comprises:

identifying a core die, the core die being an electrically malfunctioning die surrounded by a plurality of other electrically malfunctioning dice; and

locating an electrically malfunctioning die located adjacent to an edge of the core die.

3. The method of claim 1 wherein the first tier of buffer dice are located adjacent to an edge of the one or more failed dice.

4. The method of claim 1 wherein the first tier of buffer dice are located diagonally adjacent to the one or more failed dice.

5. The method of claim 3 further comprising adding a second tier of buffer dice to the weighted character map edgewise adjacent to each of the first tier of buffer dice on the weighted character map.

6. The method of claim 5 wherein the second tier of buffer dice are located adjacent to an edge of the first tier of buffer dice.

7. The method of claim 5 further comprising adding a third tier of buffer dice to the weighted character map adjacent to each of the second tier of buffer dice on the weighted character map.

8. The method of claim 7 wherein the third tier of buffer dice are located adjacent to an edge of the second tier of buffer dice.

9. The method of claim 7 further comprising adding a fourth tier of buffer dice to the weighted character map adjacent to each of the third tier of buffer dice on the weighted character map.

10. The method of claim 9 wherein the fourth tier of buffer dice are located adjacent to an edge of the third tier of buffer dice.

11. The method of claim 9 wherein the first tier of buffer dice are located diagonally adjacent to the third tier of buffer dice.