Expeditious and low cost testing of RFID ICs

• US 20060226864A1
• Filed: 04/06/2005
• Published: 10/12/2006
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kramer, Bradley Allen
• Granted Patent: US 7,279,920 B2
• Time in Patent Office: Days
• US Class Current: 324/750.150
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a second set of data to the ICs and having the ICs compare the second set of data with the first set of data stored in the memory, reading out the results of the comparisons, and marking an IC as being defective if the comparison indicates that that the first set of data did not match the second set of data. Each IC features an antenna formed in the scribe line region adjacent to the IC so that communications can take place while the IC remains on the wafer without the need to use electrical probes.

Claims

1. A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising:

transmitting a first instruction and a first set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the first set of data into the memory;

transmitting a second instruction and a second set of data to the on-wafer ICs, wherein the second instruction commands the on-wafer ICs to compare the second set of data with the first set of data stored in the memory;

reading out results of the comparisons; and

marking a status of each on-wafer IC based on the result of the comparison associated with the on-wafer IC being marked.

2. The method of claim 1, wherein the first set of data and the second set of data are the same, and wherein the marking comprises marking the on-wafer IC defective if the comparison indicates that the first set of data differs from the second set of data.

3. The method of claim 2 further comprising after the marking, cutting out the on-wafer ICs and discarding the on-wafer ICs marked as defective.

4. The method of claim 1 further comprising, at each on-wafer IC, storing a result of the comparison to a specified memory location.

5. The method of claim 1, wherein the reading out comprises the use of electrical probes that make contact with input/output pads on each on-wafer IC to read out the result of the comparison.

6. The method of claim 5, wherein the reading out further comprises writing a unique identifier to each on-wafer IC.

7. The method of claim 1, wherein each on-wafer IC has a unique identifier, and wherein the reading out comprises, at each on-wafer IC, transmitting a result of the comparison.

8. The method of claim 7, wherein transmissions from each on-wafer is labeled with the unique identifier.

9. The method of claim 7, wherein the unique identifier is hardwired into each on-wafer IC.

10. A method for testing on-wafer integrated circuits (ICs), wherein each on-wafer IC contains an antenna and a memory, the method comprising:

transmitting a first instruction and a set of data to the on-wafer ICs, wherein the first instruction commands the on-wafer ICs to store the set of data into memory;

transmitting a transmit command to the on-wafer ICs;

receiving the set of data from each on-wafer IC;

comparing the set of data from each on-wafer IC with a copy of the set of data; and

marking a status of each on-wafer IC based on the result of the comparison.

11. The method of claim 10 further comprising prior to the first transmitting, writing a unique identifier to each on-wafer IC.

12. The method of claim 11, wherein the writing is performed during testing using electrical probes making contact with input/output pads on each on-wafer IC.

13. The method of claim 11, wherein the writing occurs during the manufacture of the on-wafer ICs.

14. The method of claim 10, wherein each on-wafer IC has a unique identifier, and wherein transmissions from each on-wafer IC is labeled with the unique identifier.

15. The method of claim 14, wherein transmissions from each on-wafer IC are made so that transmission collisions do not occur.

16. The method of claim 10, wherein an on-wafer IC is marked defective if the comparison of the set of data from the on-wafer IC and the copy of the set of data does not match, the method further comprising after the marking, cutting out the on-wafer ICs and discarding the on-wafer ICs with a defective status.

17. The method of claim 10, wherein the transmit command instructs each on-wafer IC to transmit the set of data stored in its memory.

18. An on-wafer integrated circuit (IC) made for on-wafer testing, the on-wafer IC comprising:

an integrated circuitry portion containing circuitry to perform desired operations of the on-wafer IC; and

an antenna coupled to the integrated circuitry portion, the antenna formed in a scribe line region of a semiconductor wafer, the antenna to permit circuitry in the integrated circuitry portion of the on-wafer IC to communicate prior to being cut out from the semiconductor wafer.

19. The on-wafer IC of claim 18, wherein there are a plurality of the on-wafer ICs on the semiconductor wafer, and each on-wafer IC has a distinct antenna.

20. The on-wafer IC of claim 18, wherein the on-wafer IC is capable of deriving power from radio-frequency transmissions received at its antenna.

21. The on-wafer IC of claim 18, wherein when the on-wafer IC is cut out from the semiconductor wafer, the antenna is destroyed.

22. The on-wafer IC of claim 18, wherein the on-wafer IC is for use in a radio-frequency identification (RFID) tag.