Magnetically differential inductors and associated methods

• US 20060226943A1
• Filed: 03/30/2005
• Published: 10/12/2006
• Est. Priority Date: 03/30/2005
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Marques, Augusto Manuel
• Application Number:
  US11/094,834
• Publication Number:
  US 20060226943A1
• Time in Patent Office: Days
• US Class Current: 335/285
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 27/346 Preventing or reducing leakage fields using magnetic shields H01F27/36; using auxiliary windings H01F27/38
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/0233 Filters, inductors or a magnetic substance
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/09254 Branched layout

Abstract

A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Claims

1. A circuit formed on an integrated circuit comprising:

an inductor formed by first and second conductive loops coupled in series with each other; and

wherein the first and second conductive loops are configured such that magnetic field generated by the first conductive loop at least partially cancels the magnetic field generated by the second conductive loop.

2. The circuit of claim 1, wherein magnetic fields generated by the first and second conductive loops are at least partially canceled by configuring the first and second conductive loops such that current flows in opposite directions through the first and second conductive loops.

3. The circuit of claim 2, wherein the first and second conductive loops define a first axis extending through the approximate centers of the first and second conductive loops, and a second axis perpendicular to the first axis, and wherein magnetic cancellation is greatest along the second axis.

4. The circuit of claim 3, further comprising digital circuitry formed on the integrated circuit, wherein the digital circuitry is positioned approximately along the second axis.

5. The circuit of claim 1, wherein the first and second conductive loops are formed in a figure-eight pattern.

6. A method of reducing interference in a circuit formed on an integrated circuit comprising:

forming an inductance using first and second inductors coupled in series, wherein the first and second inductors are arranged such that current flows through first and second inductors in opposite directions to at least partially cancel magnetic fields generated from the first and second inductors.

7. The method of claim 6, wherein the first and second inductors are each formed by a conductive loop.

8. The method of claim 7, wherein the conductive loops of the first and second inductors form a figure-eight pattern.

9. The method of claim 6, further comprising:

forming digital circuitry on the integrated circuit; and

positioning the digital circuitry on the integrated circuit at a distance and an angle relative to the first and second inductors to achieve a desired amount of mutual inductance between the first and second inductors and the digital circuitry.

10. The method of claim 6, wherein the first and second inductors define a first axis extending through the first and second inductors, and a second axis perpendicular to the first axis, the method further comprising:

providing circuitry on the integrated circuit; and

positioning the circuitry proximate the second axis to minimize interference between the inductance and the circuitry.

11. A method of reducing interference in a circuit formed on an integrated circuit comprising:

forming an inductance using first and second inductors connected in parallel, wherein the first and second inductors are arranged such that current flows through first and second inductors in opposite directions to at least partially cancel magnetic fields generated from the inductors.

12. The method of claim 11, wherein the first and second inductors are each formed by a conductive loop.

13. The method of claim 11, further comprising:

forming digital circuitry on the integrated circuit; and

positioning the digital circuitry on the integrated circuit at a distance and an angle relative to the first and second inductors to achieve a desired amount of mutual inductance between the first and second inductors and the digital circuitry.

14. The method of claim 11, wherein the first and second inductors define a first axis extending through the first and second inductors, and a second axis perpendicular to the first axis, the method further comprising:

providing circuitry on the integrated circuit; and

positioning the circuitry proximate the second axis to minimize interference between the inductance and the circuitry.

15. A circuit formed on an integrated circuit comprising:

an inductor formed by first and second conductive loops connected in parallel with each other;

wherein the first and second conductive loops are configured such that magnetic fields generated by the first conductive loop at least partially cancels magnetic fields generated by the second conductive loop.

16. The circuit of claim 15, wherein magnetic fields generated by the first and second conductive loops are at least partially canceled by configuring the first and second conductive loops such that current flows in opposite directions through the first and second conductive loops.

17. The circuit of claim 16, wherein the first and second conductive loops define a first axis extending through the approximate centers of the first and second conductive loops, and a second axis perpendicular to the first axis, and wherein magnetic cancellation is greatest along the second axis.

18. The circuit of claim 17, further comprising digital circuitry formed on the integrated circuit, wherein the digital circuitry is positioned approximately along the second axis.

19. The circuit of claim 15, wherein the first and second conductive loops are formed in a figure-eight pattern.