HYBRID FRACTIONAL-BIT SYSTEMS

• US 20060227021A1
• Filed: 03/31/2005
• Published: 10/12/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Chenming Hu, Guobiao Zhang
• Original Assignee: Chenming Hu, Guobiao Zhang
• Inventors: ZHANG, Guobiao, HU, Chenming
• Granted Patent: US 7,167,109 B2
• Time in Patent Office: Days
• US Class Current: 341/51
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03M 7/165 Conversion to or from thermometric code

Abstract

The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.

Claims

1-20. -20. (canceled)

21. A hybrid N-ary storage system, comprising:

a group of m N-ary storage cells, all cells within said group having the same number of possible states N, with N having at least two possible values N0 and N* (N0>

N*);

a configurable N-ary-to-binary encoder for converting the information stored in said group of m storage cells into n bits of binary code, said encoder being configured to an N0-ary-to-binary encoder when N=N0, and an N*-ary-to-binary encoder when N=N*;

wherein N, N0, N* represent the number of possible states for each cell, m is the number of storage cells in said group, n is the number of output binary bits from said encoder, with N, N0, N*, m, n all integers.

22. The hybrid N-ary storage system according to claim 21, wherein the maximum n=INT[log₂(N^m)] and INT[x] is the largest integer smaller than x.

23. The hybrid N-ary storage system according to claim 21, wherein said m is selected in such a way that efficiencies β

=INT[log₂(N^m)]/log₂(N^m) for both N=N0 and N=N* are ≧

90%.

24. The hybrid N-ary storage system according to claim 21, wherein said m is selected in such a way that efficiencies β

=INT[log₂(N^m)]/log₂(N^m) for both N=N0 and N=N* reach local maxima.

25. The hybrid N-ary storage system according to claim 21, wherein a selected one of said N0, N* is an integral power of 2 and the other selected one of said N0, N* is not an integral power of 2.

26. The hybrid N-ary storage system according to claim 21, wherein said encoder comprises m cell-coding blocks, each cell-coding block converting the read-out from each cell into a binary-like code.

27. The hybrid N-ary storage system according to claim 26, wherein said binary-like code is thermometer-code or quasibinary-code.

28. The hybrid N-ary storage system according to claim 21, wherein said encoder is a programmable encoder.

29. The hybrid N-ary storage system according to claim 28, wherein said encoder comprises a processor or a program.

30. The hybrid N-ary storage system according to claim 21, wherein said N or said m is programmable for said encoder.

31. The hybrid N-ary storage system according to claim 21, further comprising an N-storage element for determining the configuration of said encoder.

32. The hybrid N-ary storage system according to claim 21, wherein said storage cells are in a semiconductor memory or a disc-based storage.

33. A hybrid N-ary storage system, comprising:

first and second groups of m N-ary storage cells, all cells within either one of said first and second groups having the same number of possible states N, with N having at least two possible values N0 and N* (N0>

N*);

selection means for selecting a group from first and second groups; and

a configurable N-ary-to-binary encoder for converting the information from said selected group into n bits of binary code, said encoder being configured to an N0-ary-to-binary encoder when N=N0, and an N*-ary-to-binary encoder when N=N*;

wherein N, N0, N* represent the number of possible states for each cell, m is the number of storage cells in said group, n is the number of output binary bits from said encoder, with N, N0, N*, m, n all integers.

34. The hybrid N-ary storage system according to claim 33, wherein the maximum n=INT[log₂(N^m)] and INT[x] is the largest integer smaller than x.

35. The hybrid N-ary storage system according to claim 33, wherein said m is selected in such a way that efficiencies β

=INT[log₂(N^m)]/log₂(N^m) for both N=N0 and N=N* are ≧

90%.

36. The hybrid N-ary storage system according to claim 33, wherein said m is selected in such a way that efficiencies β

=INT[log₂(N^m)]/log₂(N^m) for both N=N0 and N=N* reach local maxima.

37. The hybrid N-ary storage system according to claim 33, wherein a selected one of said N0, N* is an integral power of 2 and the other selected one of said N0, N* is not an integral power of 2.

38. The hybrid N-ary storage system according to claim 33, wherein said first and second groups are located in a same unit-array, in different unit-arrays, or in different chips.

39. The hybrid N-ary storage system according to claim 33, wherein said encoder is located in a same chip as said cells or a different chip from said cells.

40. The hybrid N-ary storage system according to claim 33, wherein said storage cells are in a semiconductor memory or a disc-based storage.