Memory cell with trenched gated thyristor

• US 20060227601A1
• Filed: 06/01/2006
• Published: 10/12/2006
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 7,440,310 B2
• Time in Patent Office: Days
• US Class Current: 365/177
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/742 the device being a field effect transistor for turn-on or turn-off by field effect H01L29/745, H01L29/749
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge type in the storage node and storing the first charge type in a trapping insulator separating a floating body of an access transistor from the thyristor. The method further includes discharging the storage node of the memory cell, including reverse biasing the thyristor into a low conductance high impedance state, and discharging the first charge type from the storage node and discharging the first charge type from the trapping insulator. Other aspects and embodiments are provided herein.

Claims

1. A method for operating a memory cell, comprising:

charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge type in the storage node and storing the first charge type in a trapping insulator separating a floating body of an access transistor from the thyristor; and

discharging the storage node of the memory cell, including reverse biasing the thyristor into a low conductance high impedance state, and discharging the first charge type from the storage node and discharging the first charge type from the trapping insulator.

2. The method of claim 1, further comprising reading the storage node, including pulsing a gate of the access transistor and sensing a bit line for current attributed to stored charge on the storage node.

3. The method of claim 2, wherein reading the storage node includes determining that the first charge type was not stored on the storage node if current is not detected on the bit line.

4. The method of claim 2, wherein reading the storage node includes determining that the first charge type was stored on the storage node if current is detected on the bit line.

5. The method of claim 4, further comprising restoring charge on the storage node after determining the first charge type was stored on the storage node.

6. The method of claim 1, wherein storing the first charge type in the trapping insulator includes raising a potential of a floating body region of the access transistor.

7. The method of claim 1, wherein storing the first charge type in the storage node and storing the first charge type in the trapping insulator includes pulsing a gate of the access transistor and pulsing a bulk semiconductor region to a first reference potential.

8. The method of claim 1, wherein discharging the first charge type from the trapping insulator includes injecting a second charge type into a floating body of the access transistor.

9. The method of claim 1, wherein discharging the storage node of the memory cell includes storing a second charge type in the trapping insulator.

10. The method of claim 1, wherein storing the first charge type in the trapping insulator includes storing the first charge type in an oxy-nitride.

11. The method of claim 1, wherein the thyristor extends between an isolated semiconductor region and a bulk semiconductor region and is insulated from the floating body region by a thyristor gate insulator.

12. A method for operating a memory cell, comprising:

charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge type in the storage node and storing the first charge type in a trapping insulator separating a floating body of an access transistor from the thyristor;

discharging the storage node of the memory cell, including reverse biasing the thyristor into a low conductance high impedance state, and discharging the first charge type from the storage node and discharging the first charge type from the trapping insulator; and

reading the storage node, including pulsing a gate of the access transistor and sensing a bit line for current attributed to stored charge on the storage node, determining that the first charge type was not stored on the storage node if current is not detected on the bit line, and determining that the first charge type was stored on the storage node if current is detected on the bit line.

13. The method of claim 12, wherein storing the first charge type in the trapping insulator includes raising a potential of a floating body region of the access transistor.

14. The method of claim 12, wherein storing the first charge type in the storage node and storing the first charge type in the trapping insulator includes pulsing a gate of the access transistor and pulsing a bulk semiconductor region to a first reference potential.

15. The method of claim 12, wherein discharging the first charge type from the trapping insulator includes injecting a second charge type into a floating body of the access transistor.

16. The method of claim 12, wherein discharging the storage node of the memory cell includes storing a second charge type in the trapping insulator.

17. A method for operating a memory cell, comprising:

receiving a memory operation command;

in response to receiving a command to charge a storage node of the memory cell,

forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, including gating the thyristor using a floating body of an access transistor that is capacitively coupled to a gate of the access transistor, wherein gating the thyristor includes pulsing the gate of the access transistor; and

storing a first charge type in the storage node and in a trapping insulator, the trapping insulator separating the floating body of the access transistor from the thyristor;

in response to receiving a command to discharge the storage node of the memory cell,

reverse biasing the thyristor to switch the thyristor into a low conductance high impedance state, including gating the thyristor using the floating body of the access transistor, wherein gating the thyristor includes pulsing the gate of the access transistor; and

discharging the first charge type from the storage node and storing a second charge type in the trapping insulator; and

in response to receiving a read command,

pulsing the gate of the access transistor and sensing a bit line for current attributed to stored charge on the storage node of the access transistor;

if current is detected, determining that charge was stored on the storage node, and restore charge on the storage node because of a read process; and

if current is not detected, determining that charge was not stored on the storage node.

18. The method of claim 17, wherein

forward biasing a thyristor to switch the thyristor into a high conductance low impedance state and storing a first charge type in the storage node and in a trapping insulator includes:

pulsing a reference potential for a thyristor anode to a first reference potential to forward bias the thyristor;

pulsing a potential of the gate of the access transistor to gate the thyristor via the capacitively-coupled floating body; and

reducing the reference potential pulse to a second reference potential, and pulsing a bit line potential to a first bit line potential during the gate potential pulse to operate the access transistor in saturation such that the generated charge is stored in the trapping layer;

reverse biasing the thyristor to switch the thyristor into a low conductance high impedance state and discharging the first charge type from the storage node and storing a second charge type in the trapping insulator includes;

pulsing the bit line potential to the first bit line potential;

pulsing the potential of the gate of the access transistor to gate the thyristor via a capacitively-coupled floating body and to turn on the access transistor to increase the potential of the storage node with respect to the reference potential; and

pulsing the bit line potential to a second bit line potential during the gate potential pulse to forward bias a junction between the bit line and the floating body to reduce holes in the storage node and to inject electrons into the floating body and the trapping layer.

19. A method for operating a memory cell that includes an n-channel access transistor and a thyristor, the transistor including a floating body, a first diffusion region connected to a bit line, a second diffusion region to function as a storage node, and a gate separated from the floating body by a gate dielectric, the thyristor including a cathode integrally formed with the second diffusion region and an anode connected to a bulk semiconductor region, the method comprising:

storing holes in the storage node to write the memory cell into a first memory state, including;

pulsing the gate to a first gate potential, and pulsing the bulk semiconductor region to a first reference potential;

while pulsing the gate, pulsing the bit line to a first bit line potential and pulsing the bulk semiconductor to a reduced second reference potential;

removing holes from the storage node to write the memory cell into a second memory state, including;

pulsing the gate to the first gate potential; and

while pulsing the gate, pulsing the bit line to the first bit line potential followed by pulsing the bit line to a reduced second bit line potential; and

reading the memory cell, including pulsing the gate to the first gate potential and sensing the bit line for a current attributable to stored charge in the storage node.

20. The method of claim 19, wherein the first gate potential is approximately 2 volts, the first reference potential is approximately 1 volt, the reduced second reference potential is approximately 0.5 volts, the first bit line potential is approximately 2 volts, and the reduced second bit line potential is approximately—

1.5 volts.

21. The method of claim 19, further comprising storing holes in a charge trapping thyristor gate when holes are stored in the storage node, and storing electrons in the charge trapping thyristor gate when holes are removed from the storage node.