Memory architectures including non-volatile memory devices

• US 20060227605A1
• Filed: 01/03/2006
• Published: 10/12/2006
• Est. Priority Date: 01/05/2005
• Status: Abandoned Application

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Villasenor, John D., Choi, David S.
• Application Number:
  US11/325,224
• Publication Number:
  US 20060227605A1
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Architectures are described that can include integrated non-volatile memory modules. Integrated non-volatile memory modules are a form of memory that is integrated on a single chip and includes at least one volatile memory cell and at least one non-volatile memory device. Information can be loaded between the at least one memory cell and the at least one non-volatile memory device in coordination with the supply of power to the integrated non-volatile memory device. In many embodiments, the supply of power to the integrated non-volatile memory device and the loading of information between the volatile memory cells and non-volatile memory devices are controlled to conserve energy. One embodiment of the present invention includes processing circuitry connected to an integrated non-volatile memory module and a power supply connected to the processing circuitry and integrated non-volatile memory module. In addition, the integrated non-volatile memory module is integrated on a single chip and includes at least one volatile memory cell that is connected to at least one non-volatile memory device.

Claims

1. An architecture, comprising:

processing circuitry connected to an integrated non-volatile memory module; and

a power supply connected to the processing circuitry and integrated non-volatile memory module;

wherein the integrated non-volatile memory module is integrated on a single chip and includes at least one volatile memory cell that is connected to at least one non-volatile memory device.

2. The architecture of claim 1, wherein the integrated non-volatile memory module includes at least one control input that is configured to load data stored in a volatile memory cell into a non-volatile memory device.

3. The architecture of claim 2, wherein:

the processor is configured to provide a signal to the at least one control input of the integrated non-volatile memory module that causes data to be loaded from a volatile memory cell in the integrated non-volatile memory into a non-volatile memory device in the integrated non-volatile memory; and

the processor is configured to provide a signal to the power supply that causes the power supply to remove power to the volatile memory cell and the non-volatile memory device in the integrated non-volatile memory module.

4. The architecture of claim 2, wherein:

the power supply is configured to provide a signal to the at least one control input of the integrated non-volatile memory module that causes data to be loaded from a volatile memory cell in the integrated non-volatile memory module into a non-volatile memory device in the integrated non-volatile memory module; and

the power supply is configured to remove power to the volatile memory cell and the non-volatile memory device in the integrated non-volatile memory module.

5. The architecture of claim 4, wherein:

the power supply receives power from an external power source; and

the power supply is configured to sense an actual or impending interruption to the supply of power from the external power source.

6. The architecture of claim 5, wherein the power supply includes a battery as a power source in addition to the external power source.

7. The architecture of claim 1, wherein the integrated non-volatile memory module includes at least one control input that is configured to load data stored in a non-volatile memory device into a volatile memory cell.

8. The architecture of claim 7, wherein:

the processor is configured to provide a signal to the power supply that causes the power supply to provide power to a volatile memory cell and a non-volatile memory device in the integrated non-volatile memory module; and

the processor is configured to provide a signal to the at least one control input of the integrated non-volatile memory module that causes data to be loaded from the non-volatile memory device into the volatile memory cell.

9. The architecture of claim 2, wherein:

the power supply is configured to controllably supply power to a volatile memory cell and a non-volatile memory device in the integrated non-volatile memory module; and

the power supply is configured to provide a signal to the at least one control input of the integrated non-volatile memory module that causes data to be loaded from the non-volatile memory device into the volatile memory cell.

10. The architecture of claim 1, wherein the processing circuitry and integrated non-volatile memory module are connected via a bus system.

11. The architecture of claim 2, further comprising a hard disk drive connected to the processing circuitry and the integrated non-volatile memory module via the bus system.

12. The architecture of claim 11, wherein the processing circuitry includes a central processing unit.

13. The architecture of claim 10, further comprising non-volatile memory connected to the processing circuitry and the integrated NVM module via the bus system.

14. The architecture of claim 13, wherein the processing circuitry includes a video game processor.

15. The architecture of claim 10, wherein the processing circuitry includes an embedded processor.

16. The architecture of claim 1, wherein the processing circuitry and the integrated non-volatile memory module are integrated on the same chip.

17. The architecture of claim 1, wherein:

the processing circuitry includes an adaptive equalizer connected to the integrated non-volatile memory module; and

wherein the tap coefficients of the adaptive equalizer are stored in the integrated non-volatile memory module.

18. The architecture of claim 1, wherein:

the processing circuitry includes an authentication circuit connected to the integrated non-volatile memory module; and

an encryption key is stored in the integrated non-volatile memory module.

19. The architecture of claim 18, wherein:

the processing circuitry includes a psuedorandom noise generator connected to the integrated non-volatile memory module; and

wherein a psuedorandom noise authentication state and key are stored in the integrated non-volatile memory module.

20. The architecture of claim 1, wherein:

the processing circuitry includes multiple processing circuits; and

the single integrated device includes multiple integrated non-volatile memory modules that are connected to different processing circuits.

21. The architecture of claim 20, wherein:

the processing circuitry includes a convolutional encoder connected to a plurality of integrated non-volatile memory modules; and

the state of the convolution encoder is stored in the integrated non-volatile memory modules.

22. The architecture of claim 20, wherein the processing circuitry includes multiple processing circuits distributed across multiple integrated devices and a plurality of those integrated devices also include at least one integrated non-volatile memory module.

23. The architecture of claim 22, wherein:

one of the devices includes a digital signal processor and an integrated non-volatile memory module;

a second device includes a central processor unit and an integrated memory module; and

both of the devices are connected to the power supply.

24. The architecture of claim 1, further comprising:

a second integrated non-volatile memory module connected to the power supply;

wherein the processing circuitry includes;

a digital signal processor integrated on a first device;

a central processing unit integrated on a second device;

wherein the digital signal processor, the central processing unit, the first integrated non-volatile memory module and the second integrated non-volatile memory module are connected via a bus system.

25. A process for transferring information from a volatile memory cell in an integrated non-volatile memory module to an integrated memory device in the integrated non-volatile memory module where the integrated non-volatile memory module is contained on a single chip, comprising:

determining whether a portion of the integrated non-volatile memory module that includes the volatile memory cell and the integrated non-volatile device is likely to be required within a predetermined time period;

loading information in the volatile memory cell into the non-volatile device; and

removing power from the volatile memory cell and the non-volatile device.

26. The process in claim 25, further comprising:

waiting for the portion of the integrated non-volatile memory to be required;

waking up the portion of the integrated non-volatile memory; and

loading data from the non-volatile memory device into the volatile memory cell.

27. The process in claim 25, wherein determining whether a portion of the integrated non-volatile memory that includes the volatile memory cell and the integrated non-volatile device is likely to be required further comprises receiving a user instruction indicative of the portion of integrated non-volatile memory not being required.

28. The process in claim 25, wherein determining whether a portion of the integrated non-volatile memory that includes the volatile memory cell and the integrated non-volatile device is likely to be required further comprises receiving an automatically generated instruction indicative of the portion of integrated non-volatile memory not being required.

29. The process in claim 28, wherein an instruction is automatically generated when the portion of the integrated non-volatile memory has not been required for a second predetermined period of time.

30. The process of claim 29, wherein the duration of the second predetermined period of time is determined by performing analysis of the frequency with which the portion of integrated non-volatile memory is required.

31. The process of claim 25, wherein the portion of integrated non-volatile memory is an entire integrated non-volatile memory module.