Data transfer control device and electronic instrument

• US 20060227710A1
• Filed: 03/20/2006
• Published: 10/12/2006
• Est. Priority Date: 03/23/2005
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Honda, Hiroyasu
• Granted Patent: US 7,600,061 B2
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A data transfer control device includes: a link controller which analyzes a packet received through a serial bus; an interface circuit which generates interface signals and outputs the interface signals to an interface bus; and a reset signal output circuit which outputs a reset signal to the interface circuit. The link controller analyzes a packet to determine whether or not the received packet includes synchronization signal generation direction information (synchronization signal code). The reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.

Claims

1. A data transfer control device which controls data transfer, the data transfer control device comprising:

a link controller which analyzes a packet received through a serial bus;

an interface circuit which generates interface signals including a synchronization signal and outputs the interface signals to an interface bus; and

a reset signal output circuit which outputs a reset signal for the interface circuit to the interface circuit;

the link controller analyzing a packet received through the serial bus to determine whether or not the received packet includes synchronization signal generation direction information which directs the interface circuit to generate the synchronization signal; and

the reset signal output circuit outputting the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.

2. The data transfer control device as defined in claim 1,

wherein a packet received through the serial bus includes a synchronization signal code field for setting a synchronization signal code which is the synchronization signal generation direction information;

wherein the link controller analyzes the synchronization signal code field of a packet received through the serial bus to determine whether or not the synchronization signal code which directs the interface circuit to generate the synchronization signal is set in the synchronization signal code field; and

wherein the reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the synchronization signal code which directs the interface circuit to generate the synchronization signal is set in the synchronization signal code field of the received packet.

3. The data transfer control device as defined in claim 2, wherein the link controller receives a display period packet, in which data is set in a data field, through the serial bus in a display period, and receives a non-display period packet, in which data is not set in the data field, through the serial bus in a non-display period.

4. The data transfer control device as defined in claim 3, wherein, when the link controller has received the display period packet in which data is set in the data field, the link controller outputs the header including the synchronization signal code set in the packet and the data set in the packet to the interface circuit, and, when the link controller has received the non-display period packet in which data is not set in the data field, the link controller outputs the header including the synchronization signal code set in the packet to the interface circuit.

5. The data transfer control device as defined in claim 1, comprising:

an internal register in which timing information for specifying a change timing of a signal level of the interface signal output from the interface circuit is set,

wherein the interface circuit generates the interface signal of which the signal level changes at a timing according to the timing information based on the timing information set in the internal register.

6. The data transfer control device as defined in claim 5, wherein the timing information is set in the internal register based on a packet received through the serial bus.

7. The data transfer control device as defined in claim 6,

wherein the link controller receives a packet in which data is set in the data field through the serial bus after the timing information has been set in the internal register;

and

wherein the interface circuit outputs the interface signals including a signal of the data set in the packet and the synchronization signal at a timing according to the timing information set in the internal register.

8. The data transfer control device as defined in claim 1, comprising:

a packet buffer into which a packet received through the serial bus is written and which outputs an N-bit signal and a 1-bit signal,

wherein the packet buffer outputs a reset direction signal as the 1-bit signal when the link controller has determined that the received packet includes the synchronization signal generation direction information; and

wherein the reset signal output circuit outputs the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.

9. The data transfer control device as defined in claim 2, comprising:

a packet buffer into which a packet received through the serial bus is written and which outputs an N-bit signal and a 1-bit signal,

wherein the packet buffer outputs a reset direction signal as the 1-bit signal when the link controller has determined that the received packet includes the synchronization signal generation direction information; and

wherein the reset signal output circuit outputs the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.

10. The data transfer control device as defined in claim 5, comprising:

a packet buffer into which a packet received through the serial bus is written and which outputs an N-bit signal and a 1-bit signal,

wherein the packet buffer outputs a reset direction signal as the 1-bit signal when the link controller has determined that the received packet includes the synchronization signal generation direction information; and

wherein the reset signal output circuit outputs the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.

11. The data transfer control device as defined in claim 1,

wherein the interface circuit includes a counter for generating the synchronization signal;

and

wherein the counter is reset by the reset signal.

12. The data transfer control device as defined in claim 2,

wherein the interface circuit includes a counter for generating the synchronization signal;

and

wherein the counter is reset by the reset signal.

13. The data transfer control device as defined in claim 5,

wherein the interface circuit includes a counter for generating the synchronization signal;

and

wherein the counter is reset by the reset signal.

14. The data transfer control device as defined in claim 8,

wherein the interface circuit includes a counter for generating the synchronization signal;

and

wherein the counter is reset by the reset signal.

15. The data transfer control device as defined in claim 1, wherein the interface circuit outputs an RGB interface signal.

16. The data transfer control device as defined in claim 1, comprising a transceiver which transmits and receives a packet to and from a host-side data transfer control device using differential signal lines of the serial bus.

17. An electronic instrument comprising:

the data transfer control device as defined in claim 1;

and

a display driver connected with the data transfer control device through the interface bus.

18. An electronic instrument comprising:

the data transfer control device as defined in claim 2;

and

a display driver connected with the data transfer control device through the interface bus.

19. An electronic instrument comprising:

the data transfer control device as defined in claim 5;

and

a display driver connected with the data transfer control device through the interface bus.

20. An electronic instrument comprising:

the data transfer control device as defined in claim 8;

and

a display driver connected with the data transfer control device through the interface bus.