Managing queues of packets

• US 20060227788A1
• Filed: 03/29/2005
• Published: 10/12/2006
• Est. Priority Date: 03/29/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Eldar, Avigdor, Valenci, Moshe
• Application Number:
  US11/093,654
• Publication Number:
  US 20060227788A1
• Time in Patent Office: Days
• US Class Current: 370/395.400
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

Provided are a method, system, and article of manufacture for managing queues of packets. Packets are received at a network interface, wherein the received packets are capable of being processed by a plurality of processors. The received packets are stored in memory. Tasks are scheduled corresponding to selected processors of the plurality of processors. The stored packets are concurrently processed via the scheduled tasks.

Claims

1. A method, comprising:

receiving packets at a network interface, wherein the received packets are capable of being processed by a plurality of processors;

storing the received packets in memory;

scheduling tasks corresponding to selected processors of the plurality of processors; and

concurrently processing the stored packets via the scheduled tasks.

2. The method of claim 1, wherein the tasks are dispatch handlers, the method further comprising:

initiating an interrupt handler in response to receiving a packet;

determining, by the interrupt handler, the selected processors that can process the packet; and

disabling interrupts for receive queues of the selected processors prior to the scheduling of the dispatch handlers corresponding to the selected processors.

3. The method of claim 2, the method further comprising:

reading a set of packets, by a dispatch handler, from the memory;

determining selected packets from the set of packets;

processing the selected packets by a corresponding processor of the dispatch handler; and

enabling interrupts for a receive queue of the corresponding processor of the dispatch handler.

4. The method of claim 1, the method further comprising:

disabling interrupts for receive queues of the selected processors; and

enabling interrupts for a receive queue for a selected processor corresponding to a scheduled task, subsequent to processing selected packets via the scheduled task.

5. The method of claim 1, wherein an operating system that executes on the plurality of processors supports receive side scaling, and wherein the received packets are stored in at least one receive queue that is mapped to the memory.

6. The method of claim 5, wherein the tasks are dispatch handlers, wherein the plurality of processors are greater in number than the at least one receive queue, and wherein the dispatch handlers can run concurrently and process a plurality of packets from the at least one receive queue.

7. The method of claim 1, wherein cache aligned data structures are coupled to the plurality of processors for the concurrent processing of the stored packets.

8. The method of claim 1, wherein the network interface is a network adapter, wherein the plurality of processors comprise a symmetric multiprocessor machine, wherein the receiving and the storing are performed by the network adapter, wherein the scheduling of the tasks is performed by a device driver corresponding to the network adapter, and wherein different tasks execute on different processors.

9. A system, comprising:

a memory;

a network interface coupled to the memory; and

a plurality of processors coupled to the memory, wherein at least one processor of the plurality of processors is operable to;

(i) receive packets at the network interface, wherein the received packets are capable of being processed by the plurality of processors;

(ii) store the received packets in the memory;

(iii) schedule tasks corresponding to selected processors of the plurality of processors; and

(iv) concurrently process the stored packets via the scheduled tasks.

10. The system of claim 9, wherein the tasks are dispatch handlers, and wherein the at least one processor is further operable to:

initiate an interrupt handler in response to receiving a packet;

determine, by the interrupt handler, the selected processors that can process the packet; and

disable interrupts for receive queues of the selected processors prior to scheduling the dispatch handlers corresponding to the selected processors.

11. The system of claim 10, wherein the at least one processor is further operable to:

read a set of packets, by a dispatch handler, from the memory;

determine selected packets from the set of packets;

process the selected packets by a corresponding processor of the dispatch handler; and

enable interrupts for a receive queue of the corresponding processor of the dispatch handler.

12. The system of claim 9, wherein the at least one processor is further operable to:

disable interrupts for receive queues of the selected processors; and

enable interrupts for a receive queue for a selected processor corresponding to a scheduled task, subsequent to processing selected packets via the scheduled task.

13. The system of claim 9, further comprising:

an operating system that is capable of execution on the plurality of processors, wherein the operating system supports receive side scaling, and wherein the received packets are stored in at least one receive queue that is mapped to the memory.

14. The system of claim 13, wherein the tasks are dispatch handlers, wherein the plurality of processors are greater in number than the at least one receive queue, and wherein the dispatch handlers can run concurrently and process a plurality of packets from the at least one receive queue.

15. The system of claim 9, wherein cache aligned data structures are coupled to the plurality of processors for the concurrent processing of the stored packets.

16. The system of claim 9, wherein the network interface is a network adapter, wherein the plurality of processors comprise a symmetric multiprocessor machine, wherein the receiving and the storing are performed by the network adapter, wherein the scheduling of the tasks is performed by a device driver corresponding to the network adapter, and wherein different tasks execute on different processors.

17. A system, comprising:

a memory;

a video controller coupled to the memory, wherein the video controller renders graphics output;

a network interface coupled to the memory; and

a plurality of processors coupled to the memory, wherein at least one processor of the plurality of processors is operable to;

(i) receive packets at the network interface, wherein the received packets are capable of being processed by the plurality of processors;

(ii) store the received packets in the memory;

(iii) schedule tasks corresponding to selected processors of the plurality of processors; and

(iv) concurrently process the stored packets via the scheduled tasks.

18. The system of claim 17, wherein the tasks are dispatch handlers, and wherein the at least one processor is further operable to:

initiate an interrupt handler in response to receiving a packet;

determine, by the interrupt handler, the selected processors that can process the packet; and

disable interrupts for receive queues of the selected processors prior to scheduling the dispatch handlers corresponding to the selected processors.

19. The system of claim 18, wherein the at least one processor is further operable to:

read a set of packets, by a dispatch handler, from the memory;

determine selected packets from the set of packets;

process the selected packets by a corresponding processor of the dispatch handler; and

enable interrupts for a receive queue of the corresponding processor of the dispatch handler.

20. The system of claim 17, wherein the network interface is a network adapter, wherein the plurality of processors comprise a symmetric multiprocessor machine, wherein the receiving and the storing are performed by the network adapter, wherein the scheduling of the tasks is performed by a device driver corresponding to the network adapteri and wherein different tasks execute on different processors

21. An article of manufacture, comprising a storage medium having stored therein instructions capable of being executed by a machine to:

receive packets at a network interface, wherein received packets are capable of being processed by a plurality of processors;

store the received packets in memory;

schedule tasks corresponding to selected processors of the plurality of processors; and

concurrently process the stored packets via the scheduled tasks.

22. The article of manufacture of claim 21, wherein the tasks are dispatch handlers, wherein the instructions are further capable of being executed by the machine to:

initiate an interrupt handler in response to receiving a packet;

determine, by the interrupt handler, the selected processors that can process the packet; and

disable interrupts for receive queues of the selected processors prior to scheduling the dispatch handlers corresponding to the selected processors.

23. The article of manufacture of claim 22, wherein the instructions are further capable of being executed by the machine to:

read a set of packets, by a dispatch handler, from the memory;

determine selected packets from the set of packets;

process the selected packets by a corresponding processor of the dispatch handler; and

enable interrupts for a receive queue of the corresponding processor of the dispatch handler.

24. The article of manufacture of claim 21, wherein the instructions are further capable of being executed by the machine to:

disable interrupts for receive queues of the selected processors; and

enable interrupts for a receive queue for a selected processor corresponding to a scheduled task, subsequent to processing selected packets vi, the scheduled task.

25. The article of manufacture of claim 21, wherein an operating system that executes on the plurality of processors supports receive side scaling, and wherein the received packets are stored in at least one receive queue that is mapped to the memory.

26. The article of manufacture of claim 25, wherein the tasks are dispatch handlers, wherein the plurality of processors are greater in number than the at least one receive queue, and wherein the dispatch handlers can run concurrently and process a plurality of packets from the at least one receive queue.

27. The article of manufacture of claim 21, wherein cache aligned data structures are coupled to the plurality of processors for the concurrent processing of the stored packets.

28. The article of manufacture of claim 21, wherein the network interface is a network adapter, wherein the plurality of processors comprise a symmetric multiprocessor machine, wherein the receiving and the storing are performed by the network adapter, wherein the scheduling of the tasks is performed by a device driver corresponding to the network adapter, and wherein different tasks execute on different processors.