High-speed serial data transceiver and related methods
First Claim
1. A communication device on an integrated circuit (IC) chip, comprising:
- a master signal generator adapted to generate a master timing signal;
a receive-lane adapted to receive an analog serial data signal and including a sampling signal generator adapted to generate multiple time-staggered sampling signals based on the master timing signal, and multiple data paths each adapted to sample the serial data signal in accordance with a corresponding one of the time-staggered sampling signals, thereby producing multiple time-staggered data sample streams; and
a data demultiplexer module adapted to time-deskew and demultiplex the multiple time-staggered data streams.
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Accused Products
Abstract
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
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Citations
32 Claims
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1. A communication device on an integrated circuit (IC) chip, comprising:
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a master signal generator adapted to generate a master timing signal;
a receive-lane adapted to receive an analog serial data signal and including a sampling signal generator adapted to generate multiple time-staggered sampling signals based on the master timing signal, and multiple data paths each adapted to sample the serial data signal in accordance with a corresponding one of the time-staggered sampling signals, thereby producing multiple time-staggered data sample streams; and
a data demultiplexer module adapted to time-deskew and demultiplex the multiple time-staggered data streams.
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Specification