Data access and permute unit

• US 20060227966A1
• Filed: 04/08/2005
• Published: 10/12/2006
• Est. Priority Date: 04/08/2005
• Status: Active Grant

• Current Assignee: Icera Inc. (NVIDIA Corporation)
• Original Assignee: Icera Inc. (NVIDIA Corporation)
• Inventors: Knowles, Simon
• Granted Patent: US 7,933,405 B2
• Time in Patent Office: Days
• US Class Current: 380/42
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

Claims

1. A data processing unit for a computer processor, the data processing unit comprising:

register access circuitry capable of accessing one or more data operands responsive to a data access instruction;

permute circuitry capable of performing a permutation operation responsive to said data access instruction; and

execution circuitry,

said circuitry being arranged such that, in use, a permutation operation is performed in series with (i) register access and (ii) execution of a data processing operation on the or each operand accessed.

2. A data processing unit according to claim 1, wherein said circuitry is capable of accessing a single vector register operand and performing a permutation operation on said single vector register operand.

3. A data processing unit according to claim 1, wherein said circuitry is capable of accessing a plurality of vector register operands and performing a combining permutation operation on said plurality of vector register operands.

4. A data processing unit according to claim 1, wherein said circuitry is capable of performing a different permutation operation on first and second operands or operand groups.

5. A data processing unit according to claim 1, comprising a decoder capable of decoding register access information and permutation information from a single program instruction.

6. A data processing unit according to claim 5, comprising a decoder capable of decoding data processing information from said single program instruction.

7. A data processing unit according to claim 1, wherein the circuitry is configurable to perform multiple consecutive data processing operations on a data operand of a single instruction.

8. A data processing unit according to claim 1, wherein said permute circuitry is connectable between said register access circuitry and said execution circuitry such that accessed operands are supplied to said permute circuitry before being supplied to said execution circuitry.

9. A data processing unit according to claim 1, wherein said execution circuitry is connectable between said register access circuitry and said permute circuitry such that accessed operands are supplied to said permute circuitry after passing through said execution circuitry.

10. A data processing unit according to claim 1, wherein said permute circuitry and said execution circuitry are connectable such that, in use, a first permutation operation precedes execution of the data processing operation, and a second permutation operation follows execution of the data processing operation.

11. A data processing unit according to claim 1, wherein said circuitry is capable of performing a data processing operation selected from one or more of:

an arithmetic operation, a logic operation, a subsequent permutation operation, and a processor memory read or write operation.

12. A data processing unit according to claim 1, wherein the register access circuitry comprises register file read circuitry.

13. A data processing unit according to claim 1, wherein said register access circuitry comprises register file write circuitry.

14. A data processing unit according to claim 1, wherein the register access circuitry comprises a set of control inputs for determining a type of the access operation selected from plurality of access operations.

15. A data processing unit according to claim 1, wherein said permute circuitry comprises one or more of (i) a column multiplexer stage and a (ii) cross-bar multiplexer stage.

16. A data processing unit according to claim 1, wherein the permute circuitry comprises a set of control inputs determining a type of permutation operation selected from a plurality of permutation operations.

17. A data processing unit according to claim 1, wherein the permute circuitry supports permutation operation types selected from one or more of:

a roll permutation, a sort permutation, a shuffle permutation, a broadcast permutation, a select permutation, and another type of permutation.

18. A data processing unit according to claim 1 wherein the execution circuitry is capable of single instruction multiple data execution.

19. A data processing unit according to claim 1, wherein the permute circuitry is capable of performing a first type of permutation operation on a first source operand pair, and a second type of permutation operation on a second source operand.

20. A data processing unit according to claim 19, wherein the first type of permutation operation comprises a permutation from the group consisting of a roll permutation and a sort permutation.

21. A data processing unit according to claim 19, wherein the second type of permutation operation comprises a broadcast permutation.

22. A data processing unit according to claim 19, wherein a portion of said permute circuitry for performing said first type of permutation of said first source operand pair is connectable to receive first and second 64-bit source operands.

23. A data processing unit according to claim 22, wherein said portion of said permute circuitry is connectable to provide a rolled output comprising a single 64-bit result from two 64-bit source values, the 64-bit result corresponding to the source values rolled by an integer number of 16-bit half fields.

24. A data processing unit according to claim 22, wherein a portion of said permute circuitry for performing said first type of permute is connectable to provide a sort output comprising a single 64-bit result from two 64-bit values, the 64-bit result being selectable as the most significant or the least significant 64-bits of the sorted result.

25. A data processing unit according to claim 19, wherein a portion of said permute circuitry for performing said second type of permutation is connectable to provide a broadcast output repeating a selected 16-bit half-word across a plurality of 16-bit lanes in a 64-bit result.

26. A method of operating a data processing unit for a computer processor, the method comprising:

performing a permutation operation responsive to a data access instruction on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) accessing a register to obtain said at least one data operand and (ii) executing a data processing operation on said at least one data operand.

27. A method according to claim 26, wherein a permutation operation is performed on a single vector register operand.

28. A method according to claim 26, wherein a permutation operation is performed on a plurality of vector register operands.

29. A method according to claim 26, further comprising:

performing the permutation operation in series with accessing the register based on a single program instruction.

30. A method according to claim 26, further comprising:

performing multiple consecutive data processing operations on a data operand of a single instruction.

31. A method according to claim 26, wherein performing the permutation operation precedes executing the data processing operation.

32. A method according to claim 26, wherein performing the permutation operation follows executing the data processing operation.

33. A method according to claim 26, wherein a first permutation operation precedes execution of the data processing operation and a second permutation operation follows execution of the data processing operation.

34. A method according to claim 26, further comprising:

selecting the type of the permutation operation from a plurality of permutation operation types based on an opcode portion of said instruction.

35. A method according to claim 26, further comprising selecting the executed data processing operation from:

an arithmetic operation;

a logic operation;

a subsequent permutation operation; and

a processor memory read or write operation.

36. A method according to claim 26, further comprising using a set of permute control inputs to at least partly determine the type of the permutation operation selected from a plurality of permutation operation types.

37. A method according to claim 36, wherein a plurality of permutation operation types available comprises one or more selected from:

a roll permutation, a sort permutation, a shuffle permutation, a broadcast permutation, a select permutation, and another type of permutation operation.

38. A method according to claim 26, further comprising determining the value of a set of permute control inputs based on an opcode portion of the data processing instruction.

39. A method according to claim 26, wherein the data processing unit performs single instruction multiple data execution.

40. A method according to claim 26, wherein performing of the permutation and data processing operation comprises performing at least a portion of an algorithm from the group consisting of:

a Fast Fourier Transform;

Viterbi coding;

Turbo-coding;

a finite impulse response filter algorithm;

another communications algorithm.

41. A method according to claim 26, wherein a first type of permutation operation is performed on a first source operand pair, and a second type of permutation operation is performed on a second source operand.

42. A method according to claim 41, wherein performing the first type of permutation operation comprises performing a permutation from the group consisting of:

a roll permutation and a sort permutation.

43. A method according to claim 41, wherein performing the second type of permutation operation comprises performing a broadcast permutation.

44. A method according to claim 41, wherein performing one or more of the first and second types of permutation operations comprises using 64-bit data-register source arguments.

45. A method according to claim 44, wherein performing the first type of permutation operation allows performing roll operations for forming a single 64-bit result from two 64-bit source values, the 64-bit result corresponding to the source values rolled by an integer number of 16-bit elements.

46. A method according to claim 44, wherein performing the first type of permutation operation allows performing sort operations for forming a single 64-bit result from two 64-bit values, the 64-bit result being selectable as the most significant or the least significant 64-bit sort result.

47. A method according to claim 44, wherein performing the first type of permutation operation comprises performing shuffle operations for interleaving two vectors each consisting of an integer number of 16-bit elements.

48. A method according to claim 47, wherein the integer number of 16-bit elements is an integer power of two.

49. A method according to claim 44, wherein performing the second type of permutation operation allows performing a broadcast operation capable of repeating a 16-bit half-word across a plurality of 16-bit lanes in a 64-bit result.

50. A computer program product comprising program code means which include a sequence of instructions, wherein the computer program product is adapted to run on a computer such that a permutation operation, determined by at least a portion of a data access instruction of the sequence, is performed on one or more data operands accessed from a register file, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the data operand.

51. A data processing unit for a computer comprising:

a register file;

a register access and permute mechanism capable of accessing at least one data operand in said register file based on a data access instruction, said register access and permute mechanism comprising permute circuitry operable to selectively permute said accessed data operand based on a permute opcode portion of said instruction; and

a data execution pathway arranged in series with said register access and permute mechanism, said data execution pathway being operable to perform an operation on said selectively permuted data operand based on an execution opcode portion of said instruction.

52. A data processing unit as in claim 51, wherein said register access and permute mechanism comprises a decoder register file read stage connected between said register file and said execution pathway.

53. A data processing unit as in claim 52, wherein said register access and permute mechanism comprises at least one multiplexer stage connected between said decoder register file read stage and said execution pathway.

54. A data processing unit as in claim 52, wherein said register access and permute mechanism further comprises a column multiplexer stage connected between said decoder register file read stage and said execution pathway.

55. A data processing unit as in claim 52, wherein said register access and permute mechanism comprises a crossbar multiplexer stage connected between said decoder register file read stage and said execution pathway.

56. A data processing unit as in claim 52, wherein a permute control input is supplied to said decoder register file read stage.

57. A data processing unit as in claim 53, wherein a permute control input is supplied to said multiplexer stage.

58. A data processing unit as in claim 54, wherein a permute control input is supplied to said column multiplexer stage.

59. A data processing unit as in claim 55, wherein a permute control input is supplied to said crossbar multiplexer stage.

60. A data processing unit as in claim 51, comprising bypass circuitry connected between an output of said execution pathway and an input of said register file access and permute mechanism.

61. A data processing unit as in claim 51, comprising first and second register access and permute circuitry.

62. A data processing unit as in claim 61, wherein said first register access and permute circuitry is arranged to access first and second operands and to perform a permutation selected from one or more of a roll, a sort, a shuffle.

63. A data processing unit as in claim 61, wherein said second register access and permute circuitry is arranged to access at least one operand and to perform a broadcast permutation.

64. A data processing unit as in claim 61, wherein said first and second register access and permute circuits each comprises one or more of:

(i) a decoder register file read stage connected between said register file and said execution pathway;

(ii) at least one multiplexer stage connected between said decoder register file read stage and said execution pathway.

65. A data processing unit as in claim 64, wherein said at least one multiplexer stage comprises one or more of:

(i) a column multiplexer stage connected between said decoder register file read stage and an execution pathway; and

(ii) a crossbar multiplexer stage connected between said column multiplexer stage and said execution pathway.

66. A data processing unit as in claim 51, wherein said execution pathway comprises SIMD circuitry.

67. An instruction comprising;

(i) a data access opcode portion defining a type of data access;

(ii) a permute opcode portion defining a type of permute operation;

(iii) a execution opcode portion defining further operation; and

at least one data operand source designation.

68. A data processing unit for a computer processor comprising, in series connectivity, a register access unit, vector permutation circuitry, and at least one execution pathway, the apparatus further comprising a decode unit operable, responsive to a single in instruction, to control access to at least one vector operand, to selectively permute the at least one vector operand, and to execute at least one further operation.