Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus
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Abstract
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.
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Citations
71 Claims
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1-34. -34. (canceled)
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35. A signal processing circuit comprising:
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an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, said arithmetic processing circuit comprising a plurality of arithmetic processing blocks, each of said arithmetic processing blocks comprising an adaptive processing block capable of changing a processing function including signal modulation for the input signal on the basis of a control signal contained in the arrangement control signal and a plurality of switch blocks arranged between signal lines for connecting said adaptive processing block and another arithmetic processing block to connect/disconnect the signal lines on the basis of the control signal contained in the arrangement control signal, wherein said arithmetic processing circuit realizes the different signal processing functions by controlling said switch blocks and said adaptive processing blocks in accordance with the arrangement control signal from said arrangement control means, wherein said arrangement control means controls said switch blocks and said adaptive processing block by the arrangement control signal at a timing based on arithmetic results from said plurality of arithmetic processing blocks, wherein said arrangement control means outputs the arrangement control signal at a timing after an elapse of a predetermined time from when a sum value of the arithmetic results from said adaptive processing block, which are input to said arrangement control means, exceeds a predetermined value, and wherein when said adaptive processing block has a refractory period, and the refractory period is larger than a difference in input signal arrival time at some or all adaptive processing blocks belonging to a single layer, the predetermined time is not less than the refractory period.
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36. A signal processing circuit comprising:
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an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, said arithmetic processing circuit comprising a plurality of arithmetic processing blocks, each of said arithmetic processing blocks comprising an adaptive processing block capable of changing a processing function including signal modulation for the input signal on the basis of a control signal contained in the arrangement control signal and a plurality of switch blocks arranged between signal lines for connecting said adaptive processing block and another arithmetic processing block to connect/disconnect the signal lines on the basis of the control signal contained in the arrangement control signal, wherein said arithmetic processing circuit realizes the different signal processing functions by controlling said switch blocks and said adaptive processing blocks in accordance with the arrangement control signal from said arrangement control means, wherein said arrangement control means controls said switch blocks and said adaptive processing block by the arrangement control signal at a timing based on arithmetic results from said plurality of arithmetic processing blocks, and wherein said arrangement control means controls an arithmetic value of weighted addition processing or weighted integration processing for a predetermined adaptive processing block at a timing based on the arithmetic result. - View Dependent Claims (37)
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38. (canceled)
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39. A signal processing circuit comprising:
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an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, wherein said circuit further comprises a signal input circuit for time divisionally inputting signals from a plurality of signal sources, said arrangement control means determines connection between the plurality of signal sources and said arithmetic processing circuit to realize an interconnection structure, said signal input circuit inputs the signals from the plurality of signal sources to said arithmetic processing circuit through the connection determined by said arrangement control means, and said arithmetic circuit regenerates some or all of the input signals and executes predetermined signal processing for the regenerated signals. - View Dependent Claims (40)
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41. (canceled)
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42. A pattern recognition apparatus comprising:
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input means for inputting pattern data; and
a signal processing circuit comprising;
an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, said arithmetic processing circuit comprises a plurality of arithmetic processing blocks, each of said arithmetic processing blocks comprises an adaptive processing block capable of changing a processing function including signal modulation for the input signal on the basis of a control signal contained in the arrangement control signal, and a plurality of switch blocks arranged between signal lines for connecting said adaptive processing block and another arithmetic processing block to connect/disconnect the signal lines on the basis of the control signal contained in the arrangement control signal, and said arithmetic processing circuit realizes the different signal processing functions by controlling said switch blocks and said adaptive processing blocks in accordance with the arrangement control signal from said arrangement control means, and wherein a pulse signal corresponding to a feature of the pattern data is modulated in said arithmetic processing block in accordance with a detection category, thereby hierarchically detecting lower to higher order features and executing pattern recognition of the pattern data.
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43-45. -45. (canceled)
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46. A pattern recognition apparatus comprising:
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time-division data input means for time serially inputting pattern data having a predetermined size as part of input data a plurality of number of times;
position information input means for inputting position information of the pattern data on the input data;
feature detection means, having a processing circuit, for detecting predetermined medium or higher order features related to a predetermined category from the pattern data;
time serial integration processing means for time serially integrating outputs from said feature detection means on the basis of the position information and the feature category to generate feature detection map information; and
determination means for outputting position information of the higher order feature in the input data and the category information on the basis of an output from said time serial integration processing means, wherein said processing circuit comprises;
an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, and said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, and wherein said time division data input means scans and inputs data in a block region having a predetermined size from the input data, and further comprising scan control means for updating a scanning position of said data input means on the basis of a predetermined matching value with a higher order pattern to be detected, which is obtained by said integration means. - View Dependent Claims (47, 48)
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49. A pattern recognition apparatus comprising:
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time-division data input means for time serially inputting pattern data having a predetermined size as part of input data a plurality of number of times;
position information input means for inputting position information of the pattern data on the input data;
feature detection means, having a processing circuit, for detecting predetermined medium or higher order features related to a predetermined category from the pattern data;
time serial integration processing means for time serially integrating outputs from said feature detection means on the basis of the position information and the feature category to generate feature detection map information; and
determination means for outputting position information of the higher order feature in the input data and the category information on the basis of an output from said time serial integration processing means, wherein said processing circuit comprises;
an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, and said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, wherein said circuit arrangement control means time serially updates the arithmetic characteristic of said arithmetic processing circuit. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. An image processing apparatus for controlling input operation of an image to be processed, on the basis of an output signal corresponding to a result of processing of a signal representing the image to be processed using a pattern recognition apparatus comprising:
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time-division data input means for time serially inputting pattern data having a predetermined size as part of input data a plurality of number of times;
position information input means for inputting position information of the pattern data on the input data;
feature detection means, having a processing circuit, for detecting predetermined medium or higher order features related to a predetermined category from the pattern data;
time serial integration processing means for time serially integrating outputs from said feature detection means on the basis of the position information and the feature category to generate feature detection map information; and
determination means for outputting position information of the higher order feature in the input data and the category information on the basis of an output from said time serial integration processing means, wherein said processing circuit comprises;
an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, and said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal.
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61. An image processing apparatus comprising:
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image input means; and
image processing means for time serially executing a plurality of spatial filter arithmetic operations for single image data input from said image input means in correspondence with a plurality of different spatial filter characteristics. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71)
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Specification