Vicinal gallium nitride substrate for high quality homoepitaxy

• US 20060228584A1
• Filed: 05/11/2006
• Published: 10/12/2006
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: George R. Brandes, Jeffrey S. Flynn, Robert P. Vaudo, Xueping Xu
• Inventors: Brandes, George R., Xu, Xueping, Vaudo, Robert P., Flynn, Jeffrey S.
• Granted Patent: US 7,390,581 B2
• Time in Patent Office: Days
• US Class Current: 428/698
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: Y10T 428/31 Surface property or characteristic of web, sheet or block
• CPC Class Codes: Y10T 83/0524 Plural cutting steps

Abstract

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm² AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm⁻². The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Claims

1. A GaN substrate including a GaN (0001) surface offcut from the <

0001>

direction predominantly towards a direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions, at an offcut angle in a range that is from 2 to 5 degrees, wherein said surface has a RMS roughness measured by 50×

50 μ

m² AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm<sup>−

2</sup>.

2. The GaN substrate of claim 1, wherein the GaN (0001) surface is offcut predominantly toward the <

10{overscore (1)}0>

direction.

3. The GaN substrate of claim 1, wherein the GaN (0001) surface is offcut predominantly toward the <

11{overscore (2)}0>

direction.

4. The GaN substrate of claim 1, wherein the GaN (0001) surface is offcut at an offcut angle in a range that is between 2 degrees and about 4 degrees.

5. The GaN substrate of claim 1, wherein said surface has a RMS roughness measured by 50×

50 μ

m² AFM scan that is less than 0.9 nm.

6. The GaN substrate of claim 1, wherein said surface has a RMS roughness measured by 50×

50 μ

m² AFM scan that is less than 0.5 nm.

7. The GaN substrate of claim 1, wherein said surface has a dislocation density that is less than 1E6cm⁻

2.

8. The GaN substrate of claim 1, wherein said surface has a dislocation density that is less than 5E5 cm⁻

2.

9. A microelectronic or opto-electronic device article, comprising a GaN substrate as claimed in any of the preceding claims, and a microelectronic or opto-electronic device structure including a homoepitaxial GaN layer deposited on said surface.

10. The device article of claim 9, wherein said device structure comprises a device selected from the group consisting of laser diodes, light emitting devices, transistors, diodes, and detectors.

11. The device article of claim 9, wherein said device structure comprises a blue or shorter wavelength laser diode, or an HEMT device.

12. A method of forming a GaN substrate including a GaN (0001) surface offcut from the <

0001>

direction predominantly towards a direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions, at an offcut angle in a range that is from 2 to 5 degrees, wherein said surface, has a RMS roughness measured by 50×

50 μ

m² AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm<sup>−

2</sup>, said method including growing a bulk GaN single crystal body, and processing said bulk GaN single crystal body to form at least one wafer therefrom, wherein said processing step includes a step selected from the group consisting of;

(i) a slicing step conducted in a slicing plane tilted away from the c-plane at said offcut angle in said direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions,

(ii) an angle lapping step conducted in a lapping plane tilted away from the c-plane at said offcut angle in said direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions, and

(iii) separating said bulk GaN single crystal body after growing said bulk GaN single crystal body on a vicinal heteroepitaxial substrate including a (0001) surface offcut from the <

0001>

direction predominantly towards a direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions, at an offcut angle in said range of from 2 to 10 degrees.

13. The method of claim 12, wherein said at least one wafer is finished by at least one finishing step selected from the group consisting of lapping, polishing and chemical mechanical polishing.

14. The method of claim 12, wherein said processing step includes step (i).

15. The method of claim 12, wherein said processing step includes step (ii).

16. The method of claim 12, wherein said processing step includes step (iii).

17. The method of claim 12, wherein said vicinal heteroepitaxial substrate comprises a material selected from the group consisting of sapphire and GaAs.

18. The method of claim 12, wherein said offcut angle range is from 2 to 4 degrees.

19. The method of claim 12, wherein said offcut angle range is from 2.5 to 10 degrees.

20. The method of claim 12, wherein said offcut angle range is from 5 to 8 degrees.

21. A method of fabricating a microelectronic or opto-electronic device, comprising the steps of:

(c) forming a GaN substrate according to the method of claim 12;

and

(d) depositing on said GaN substrate a homoepitaxial III-V nitride material.

22. The method of claim 21, wherein said step of depositing a homoepitaxial III-V nitride material comprises MOVPE.

23. The method of claim 21, wherein said depositing step is carried out at a temperature in a range of from 1100 to 1225°

C.

24. The method of claim 21, wherein said depositing step is carried out at a temperature in a range of from 1120 to 1170°

C.

25. The method of claim 21, wherein said depositing step is carried out at a temperature in a range of from 700 to 1220°

C.

26. The method claim 21, wherein said depositing step is carried out at growth rate in a range of from 0.1 μ

m/hr to 50 μ

m/hr.

27. The method claim 21, wherein said depositing step is carried out at growth rate in a range of from 1 μ

m/hr to 4 μ

m/hr.

28. The method of claim 21, wherein said depositing step is carried out at growth rate in a range of from about 2 μ

m/hr to about 4 μ

m/hr.

29. The method of claim 21, wherein said homoepitaxial III-V nitride material contains GaN.

30. The method of claim 29, further comprising depositing an AlGaN material on the GaN-containing homoepitaxial III-V nitride material, to form an AlGaN/GaN HEMT.

31. A non-light-emitting electronic device structure comprising a GaN substrate including a GaN (0001) surface offcut from the <

0001>

direction predominantly towards a direction selected from the group consisting of <

10{overscore (1)}0> and

<

11{overscore (2)}0>

directions, at an offcut angle in a range that is from 0.2 to 10 degrees, wherein said surface has a RMS roughness measured by 50×

50 μ

m² AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm<sup>−

2</sup>.

32. A non-light-emitting microelectronic device article selected from the group consisting of transistors, diodes, and detectors, comprising the structure of claim 31.

33. A high electron mobility transistor including the structure of claim 31.

34. The structure of claim 31, wherein the GaN (0001) surface is offcut at an offcut angle in a range of from about 2 to about 4 degrees.

35. The structure of claim 31, wherein the GaN (0001) surface is offcut at an offcut angle in a range of from about 5 to about 8 degrees.