Contact scheme for memory array and manufacturing methods thereof

• US 20060228859A1
• Filed: 04/11/2005
• Published: 10/12/2006
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Willer, Josef
• Granted Patent: US 7,256,098 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling layer running in a first direction. A layer of dielectric material is deposited on the first conductive lines. A control gate layer is deposited. The first conductive lines are patterned to produce gate stacks. Dielectric material is deposited in between the gate stacks. The gate stacks are partially removed to uncover floating gate electrodes in region of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction. The selection transistor line recesses are filled with a conductive material to create the selection transistor lines.

Claims

1. A method of manufacturing a memory device comprising:

providing a substrate having a tunneling layer deposited on a main surface and having first conductive lines arranged on the tunneling layer running in a first direction;

depositing a layer of dielectric material on the first conductive lines;

depositing of a control gate layer;

patterning the first conductive lines to produce gate stacks;

depositing dielectric material in between the gate stacks;

partially removing the gate stacks to uncover floating gate electrodes in regions of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction; and

filling the selection transistor line recesses with a conductive material to create the selection transistor lines.

2. The method of claim 1, further comprising:

selectively uncovering the substrate in a region of source lines to be prepared to create source line recesses running in the second direction; and

filling the source line recesses with a conductive, metallic material to create the source lines.

3. The method of claim 1, further comprising:

selectively uncovering the substrate in a region of bit line contacts to be prepared to create bit line recesses; and

filling the bit line recesses with conductive, metallic material to create the bit line contacts.

4. A method of manufacturing a flash memory device comprising a NAND-array of floating gate memory cells comprising:

providing a substrate of semiconductor material having a layer of dielectric material provided as a tunneling dielectric layer deposited on a main surface and having first conductive lines of electrically conductive material arranged on the tunneling oxide layer running in a first direction;

depositing a layer of dielectric material provided as a coupling dielectric layer on the first conductive lines;

depositing of electrically conductive material provided as a control gate layer;

patterning the control gate layer in a second direction crossing the first direction to produce second conductive lines in a region of memory transistors and selection transistors to be prepared, thereby patterning the first conductive lines to produce gate stacks;

depositing dielectric material in between the gate stacks;

partially removing the gate stacks to uncover the floating gate electrodes in regions of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction; and

filling the selection transistor line recesses with a conductive, metallic material to create the selection transistor lines.

5. The method of claim 4, further comprising:

selectively uncovering the substrate in a region of source lines to be prepared to create source line recesses running in the second direction; and

filling the source line recesses with a conductive, metallic material to create the source lines.

6. The method of claim 4, further comprising:

selectively uncovering the substrate in a region of bit line contacts to be prepared to create bit line recesses; and

filling the bit line recesses with conductive, metallic material to create the bit line contacts.

7. The method of claim 4, wherein the selection transistor line recesses and source line recesses are filled with conductive material at the same time.

8. The method of claim 4, wherein the first conductive lines provided in the substrate is prepared in a self-aligned manner.

14. The method of claim 4, wherein before the deposition of dielectric material in between the gate stacks comprising implanting one or more dopants into the substrate in between the gate stacks.

15. The method of claim 4, wherein before the filling of the selection transistor line recesses with conductive, metallic material to create the selection transistor lines comprising implanting one or more dopants into the floating gates.

16. The method of claim 5, wherein before the filling of the source line recesses with conductive, metallic material to create source lines comprising implanting one or more dopants into the substrate.

17. The method of claim 6, wherein before the filling of the bit line contact recesses with conductive, metallic material to create the bit line contacts comprising implanting one or more dopants into the substrate.

9. A method of manufacturing a flash memory device comprising a NAND array of floating gate memory cells for producing selection transistor lines and source lines, comprising:

providing a substrate of semiconductor material having a layer of dielectric material provided as tunneling dielectric layer deposited on a main surface thereof and having first conductive lines of electrically conductive material arranged on the tunneling oxide layer running in a first direction;

depositing a layer of dielectric material provided as a coupling dielectric layer on the first conductive lines;

depositing of electrically conductive material as a control gate layer;

patterning the control gate layer in a second direction crossing the first direction to produce second conductive lines in regions of memory transistors, selection transistors and source lines to be prepared, thereby patterning the first conductive lines to produce gate stacks;

depositing of dielectric material in between the gate stacks;

partially removing the gate stacks to uncover the floating gate electrodes in regions of selection transistor lines and source lines, respectively, to be prepared creating selection transistor line recesses and first source line recesses, respectively, running in the second direction;

totally removing the gate stacks to uncover the substrate in regions of source lines to be prepared creating second source line recesses running in the second direction; and

filling the selection transistor line recesses and the second source line recesses with conductive metallic material to create the selection transistor lines and source lines.

10. The method of claim 9, further comprising:

selectively uncovering the substrate in a region of bit line contacts to be prepared to create bit line recesses;

filling the bit line contact recesses with conductive, metallic material to create the bit line contacts.

11. The method of claim 9, wherein the first conductive lines provided in the substrate are prepared in a self-aligned manner.

12. A method of manufacturing a flash memory device comprising a NAND array of floating gate memory cells, including producing selection transistor lines, source lines and bit line contacts, comprising:

providing a substrate of semiconductor material having a layer of dielectric material provided as tunneling dielectric layer deposited on a main surface thereof and having first conductive lines of electrically conductive material arranged on the tunneling oxide layer running in a first direction;

depositing a layer of dielectric material that is provided as coupling dielectric layer on the first conductive lines;

depositing of electrically conductive material provided as control gate layer;

patterning the control gate layer in a second direction crossing the first direction to produce second conductive lines in regions of memory transistors, selection transistors, source lines and bit line contacts to be prepared, thereby patterning the first conductive lines to produce gate stacks;

depositing of dielectric material in between the gate stacks;

partially removing the gate stacks to uncover the floating gate electrodes in regions of selection transistor lines, source lines and bit line contacts, to be prepared creating selection transistor line recesses, first source line recesses and first bit line contact recesses, running in the second direction;

totally removing the gate stacks to uncover the substrate in regions of source lines and bit line contacts, respectively, to be prepared creating second source line recesses and second bit line contact recesses, respectively, running in the second direction; and

filling the selection transistor line recesses, the second source line recesses and second bit line recesses, respectively, with conductive, in particular metallic material to create the selection transistor lines, source lines and bit line contacts, respectively.

13. The method of claim 12, wherein the first conductive lines provided in the substrate are prepared in a self-aligned manner.

18. A flash memory device comprising:

a NAND-array of floating gate memory cells, the memory cells being arranged in NAND-strings, each NAND-string comprising a serial connection of floating gate memory transistors and at least one selection transistor for the selection thereof, the NAND-string being electrically interconnected between a bit line running in a first direction and a source line running in a second direction crossing the first direction, the memory transistors having control gate electrodes being in electric contact with word lines running in the second direction, the selection transistor having a control gate electrode being in electric contact with a selection transistor line being in parallel alignment to the word lines, wherein the selection transistor lines are made of metallic material.

19. The flash memory device of claim 18, wherein the source lines are made of metallic material.

20. The flash memory device of claims 18, wherein the bit line contacts are made of metallic material.

21. A method of manufacturing a flash memory device comprising:

a NAND array of floating gate memory cells the memory cells being arranged in NAND-strings, each NAND-string comprising a serial connection of floating gate memory transistors and at least one selection transistor for the selection thereof, the NAND-string being electrically interconnected between a bit line running in a first direction and a source line running in a second direction crossing the first direction, the memory transistors having control gate electrodes being in electric contact with word lines running in the second direction, the selection transistor having a control gate electrode being in electric contact with a selection transistor line being in parallel alignment to the word lines, the method comprising;

providing a substrate of semiconductor material having a layer of dielectric material provided as tunneling dielectric layer deposited on a main surface thereof and having lines of electrically conductive material provided as floating gate lines arranged on the tunneling oxide layer running in the first direction;

depositing a layer of dielectric material that is provided as coupling dielectric layer on the floating gate lines;

depositing at least one layer of electrically conductive material provided as control gate layer;

patterning the control gate layer in the second direction to produce word lines that provide control gate electrodes;

patterning the floating gate lines to produce gate stacks;

depositing a layer of dielectric material on the floating gate stacks to electrically isolate the floating gate stacks;

selectively uncovering the floating gate electrodes in regions of selection transistor lines to be prepared creating a selection transistor line trench running in the second direction;

selectively uncovering the substrate in a region of source lines to be prepared to create source line trenches running in the second direction;

filling the selection transistor line trenches with conductive, in particular metallic material to create the selection transistor lines;

filling the source line trenches with metallic material to create the source lines;

depositing a layer of dielectric material at least on the selection transistor and source lines; and

manufacturing of the bit lines, each one being in electric contact with at least one NAND-string.