Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process

• US 20060228864A1
• Filed: 04/12/2005
• Published: 10/12/2006
• Est. Priority Date: 04/12/2005
• Status: Abandoned Application

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Chen, Hsi-Chieh, Chen, Chuan-Chi
• Application Number:
  US11/103,948
• Publication Number:
  US 20060228864A1
• Time in Patent Office: Days
• US Class Current: 438/400
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The storage capacitor is formed from a bottle-shaped trench and having an Epi-Si layer grown inside the trench to form at least part of one of the source and drain regions. The Epi-Si layer can be selectively grown inside the trench from portions of the substrate such that the Epi-Si layer is used to define a bottle-shape for the trench.

Claims

1. A semiconductor fabrication method comprising:

forming a trench in a substrate; and

forming an Epi-Si layer from portions of the substrate such that the Epi-Si layer is used to define a bottle-shape for the trench.

2. The method of claim 1, wherein forming the trench includes forming a deep trench.

3. The method of claim 2, further comprising:

forming a buried plate in the substrate by diffusing dopants from a dopant layer formed in the deep trench.

4. The method of claim 3, further comprising:

forming a capacitor node dielectric layer in the deep trench;

forming a first polysilicon layer in the deep trench;

forming a collar oxide layer over the first polysilicon layer and capacitor node dielectric layer;

forming a second polysilicon layer on the first polysilicon layer; and

forming a third polysilicon layer over the second polysilicon layer.

5. The method of claim 4, wherein the first, second, and third polysilicon layers act as storage node, node connector, and capping node layers, respectively.

6. The method of claim 5, further comprising:

forming an electrical connection between a transistor and the capping node layers.

7. A semiconductor device comprising:

a substrate with a trench formed therein; and

an Epi-Si layer formed from portions of the substrate such that the Epi-Si layer is used to define a bottle-shape for the trench.

8. The semiconductor device of claim 7, wherein the trench includes a deep trench.

9. The semiconductor device of claim 8, further comprising:

a buried plate formed in the substrate from dopants diffused from a dopant layer formed in the deep trench.

10. The semiconductor device of claim 9, further comprising:

a capacitor node dielectric layer formed in the deep trench;

a first polysilicon layer formed in the deep trench;

a collar oxide layer formed over the first polysilicon layer and capacitor node dielectric layer;

a second polysilicon layer formed on the first polysilicon layer; and

a third polysilicon layer formed over the second polysilicon layer.

11. The semiconductor device of claim 10, wherein the first, second, and third polysilicon layers include storage node, node connector, and capping node layers, respectively.

12. The semiconductor device of claim 11, further comprising:

forming an electrical connection between a transistor and at least the capping node layer.

13. A semiconductor device comprising:

a transistor having source and drain regions formed on a substrate; and

a storage capacitor coupled to the transistor, the storage capacitor formed from a bottle-shaped trench and having and an Epi-Si layer grown inside the trench to form at least part of one of the source and drain regions.

14. The semiconductor device of claim 13, wherein the Epi-Si layer is selectively grown on sidewalls of a top section of the trench.

15. The semiconductor device of claim 14, wherein the Epi-Si layer is used to define the bottle-shape for the trench.

16. The semiconductor device of claim 13, wherein the storage capacitor further comprises:

a conductive connecting layer capable of connecting with a source region of the transistor.

17. The semiconductor device of claim 16, further comprising:

one or more polysilicon layers to that form part of the conductive connecting layer.

18. A semiconductor fabrication method comprising:

forming a transistor having source and drain regions formed on a substrate; and

forming a storage capacitor coupled to the transistor, the storage capacitor formed from a bottle-shaped trench and having an Epi-Si layer grown inside the trench to form at least part of one of the source and drain regions.

19. The method of claim 18, wherein forming the storage capacitor includes growing an epitaxial layer from portions of silicon in the substrate.

20. The method of claim 19, wherein the epitaxial layer is formed from portions of the substrate that define a sidewall in a top section of the trench.