Isolation region formation that controllably induces stress in active regions

• US 20060228867A1
• Filed: 04/12/2005
• Published: 10/12/2006
• Est. Priority Date: 04/12/2005
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Taxas Instruments Incorporated
• Inventors: Mehrotra, Manoj, Zhao, Jin, Chatterjee, Amitava
• Application Number:
  US11/104,038
• Publication Number:
  US 20060228867A1
• Time in Patent Office: Days
• US Class Current: 438/435
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method (10) of forming an isolation structure (140, 142) in a semiconductor substrate (102) is disclosed, wherein the isolation structure (140, 142) can be formed in a controlled manner so as to regulate stresses exerted by the structure on one or more active regions (106) of the substrate (102) located adjacent to the structure (140, 142).

Claims

1. A method of forming an isolation structure, comprising:

forming an isolation trench in a semiconductor substrate;

forming a first layer of dielectric material over the semiconductor substrate and down into the isolation trench;

forming a second layer of dielectric material over the first layer of dielectric material;

annealing the substrate and the first and second layers of dielectric material; and

removing excess amounts of the first and second layers of dielectric material, where the annealing process causes the first layer of dielectric material to contract and thereby exert a tensile stress on one or more active regions of the semiconductor substrate that surround the isolation structure.

2. The method of claim 1, wherein the first layer of dielectric material is formed via a chemical vapor deposition (CVD) process.

3. The method of claim 2, wherein the second layer of dielectric material is formed via a high density plasma (HDP) process.

4. The method of claim 3, wherein the first layer of dielectric material comprises at least one of an oxide based material and TEOS (Tetraethyl Orthosilicate).

5. The method of claim 4, wherein the second layer of dielectric material comprises an oxide based material.

6. The method of claim 5, wherein the first layer of dielectric material is formed to a thickness of between about 50 to about 150 Angstroms.

7. The method of claim 6, wherein the second layer of dielectric material is formed to a thickness of between about 4000 to about 7000 Angstroms.

8. The method of claim 7, wherein the annealing process comprises at least one of heating to a temperature of between about 900 degrees Celsius and about 1100 degrees Celsius, and heating for a duration of between about 30 minutes and about 60 minutes.

9. The method of claim 8, wherein the second layer of dielectric material exerts a compressive stress on the active regions.

10. The method of claim 9, wherein the excess dielectric material is removed via a chemical mechanical polishing (CMP) process.

11. The method of claim 10, wherein the annealing process is performed after the first layer of dielectric material is formed, but prior to forming the second layer of dielectric material to reduce the tensile stress exerted on the active regions.

12. The method of claim 10, wherein a net compressive stress is exerted on the active regions and the tensile stress exerted by the first dielectric layer merely mitigates the compressive stress.

13. The method of claim 10, wherein excess dielectric material is removed prior to the annealing process.

14. The method of claim 10, wherein the tensile stress exerted on the active regions enhances electron mobility.

15. An isolation structure formed within a semiconductor substrate adjacent to an active region of the semiconductor substrate, the isolation structure comprising:

a first layer of dielectric material formed within an isolation trench formed within the semiconductor substrate adjacent to the active region; and

a second layer of dielectric material formed over the first layer of dielectric material, where the first layer of dielectric material exerts a tensile stress on the active region.

16. The structure of claim 15, where the first layer of dielectric material exerts the tensile stress as a result of an annealing process.

17. The structure of claim 16, wherein at least one of the first layer of dielectric material is formed via a chemical vapor deposition (CVD) process and the second layer of dielectric material is formed via a high density plasma (HDP) process.

18. The structure of claim 17, wherein at least one of the first layer of dielectric material comprises at least one of an oxide based material and TEOS (Tetraethyl Orthosilicate) and the second layer of dielectric material comprises an oxide based material.

19. The structure of claim 18, wherein at least one of the first layer of dielectric material is formed to a thickness of between about 50 to about 150 Angstroms, the second layer of dielectric material is formed to a thickness of between about 4000 to about 7000 Angstroms and the annealing process comprises at least one of heating to a temperature of between about 900 degrees Celsius and about 1100 degrees Celsius, and heating for a duration of between about 30 minutes and about 60 minutes.

20. The structure of claim 19, wherein the second layer of dielectric material exerts a compressive stress on the active region.