Fabricating integrated devices using embedded masks

• US 20060228896A1
• Filed: 03/31/2005
• Published: 10/12/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Greywall, Dennis S.
• Granted Patent: US 7,410,907 B2
• Time in Patent Office: Days
• US Class Current: 438/736
• CPC Class Codes: B81B 2201/033 Comb drives
• CPC Class Codes: B81C 1/00404 Mask characterised by its size, orientation or shape

Abstract

A method of fabricating a device using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until a relatively late fabrication stage. As a result, flatness of the (poly)silicon layer is preserved for the deposition of any necessary over-layers, which substantially obviates the need for filling the voids created by the structure formation with silicon oxide.

Claims

1. A method of fabricating an integrated device, comprising:

(A) forming an embedded mask in a multi-layer wafer, the mask in contact with one or more layers of the wafer; and

(B) etching a portion of the one or more layers from the wafer, wherein the embedded mask protects other one or more portions of the one or more layers from being removed during the etching.

2. The invention of claim 1, further comprising removing the mask from the wafer after performing the etching.

3. The invention of claim 1, wherein step (A) comprises:

(A1) forming the mask over a first layer of the wafer; and

(A2) depositing a second layer over the first mask and the first layer to embed the mask into the wafer.

4. The invention of claim 3, wherein step (B) comprises front-side etching, wherein the mask protects portions of the first layer from being removed.

5. The invention of claim 3, wherein step (B) comprises backside etching, wherein the mask protects portions of the second layer from being removed.

6. The invention of claim 3, wherein the first mask comprises silicon oxide and each of the first and second layers comprises silicon.

7. The invention of claim 3, wherein at least one of the first and second layers has a thickness of at least about 10 μ

m.

8. The invention of claim 1, wherein step (A) comprises forming first and second embedded masks in a multi-layer wafer, each mask in contact with one or more layers of the wafer, wherein the one or more contact layers of first embedded mask comprise at least one layer that is not one of the one or more contact layers of the second embedded mask.

9. The invention of claim 1, wherein:

the wafer comprises a substrate layer and a plurality of layers deposited over the substrate layer; and

step (B) comprises creating an opening in the substrate layer to expose the embedded mask.

10. The invention of claim 1, wherein step (B) comprises subjecting the wafer to dry etching, wherein the embedded mask acts as an etch stop for the dry etch.

11. The invention of claim 1, wherein the embedded mask is adapted to map a structure onto at least one of the one or more contact layers and step (B) comprises forming the mapped structure.

12. The invention of claim 11, wherein the formed structure defines a via having an aspect ratio of about 5:

1 or greater.

13. The invention of claim 1, wherein step (A) comprises:

(A1) forming a first patterned mask over a substrate;

(A2) forming a second patterned mask over the substrate such that the first patterned mask is interposed between the second patterned mask and the substrate; and

(A3) depositing a layer that buries the second patterned mask, wherein the first and second masks have different patterns.

14. An integrated device, comprising:

a multi-layer wafer having a first side and a second side;

a first structure formed in a first layer of the wafer, said first structure having a first outline pattern; and

a second structure formed in a second layer of the wafer, said second structure having a second outline pattern, wherein;

the wafer has an opening in the first side, which exposes the first and second structures, said opening having a third outline pattern, wherein the third outline pattern substantially encloses the first and second outline patterns;

the second layer has a greater offset distance from the first side than the first layer; and

the second outline pattern substantially encloses the first outline pattern.

15. The invention of claim 14, further comprising a third structure formed in the second layer, said third structure having a fourth outline pattern, wherein:

the third outline pattern substantially encloses the fourth outline pattern; and

the fourth outline pattern does not overlap with the second outline pattern.

16. The invention of claim 15, wherein:

the wafer has a substrate;

the first structure is fixedly connected to the substrate; and

the third structure is movable with respect to the substrate.

17. The invention of claim 16, wherein the second structure is fixedly connected to the substrate.

18. The invention of claim 16, wherein:

the first and third structures are electrically isolated from one another;

the first and third structures are portions of a motion actuator; and

the device further comprises a plate mounted on the third structure and adapted to move with respect to the substrate.

19. The invention of claim 16, wherein the first and second structures are in electrical contact with each other and the substrate.

20. The invention of claim 14, wherein:

each of the first and second layers is a buried layer;

the first side is a backside of the wafer; and

at least one of the first and second structures defines a via having an aspect ratio of about 5;

1 or greater.