Portable cardiac monitor including pulsed power operation

• US 20060229525A1
• Filed: 04/08/2005
• Published: 10/12/2006
• Est. Priority Date: 04/08/2005
• Status: Abandoned Application

• Current Assignee: Exelys LLC
• Original Assignee: Exelys LLC
• Inventors: Barr, Keith E.
• Application Number:
  US11/101,879
• Publication Number:
  US 20060229525A1
• Time in Patent Office: Days
• US Class Current: 600/523
• CPC Class Codes: A61B 2560/0209 adapted for power saving
• CPC Class Codes: A61B 5/0006 ECG or EEG signals
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/308 for electrocardiography [ECG]
• CPC Class Codes: A61B 5/332 Portable devices specially adapted therefor
• CPC Class Codes: A61B 5/335 using integrated circuit memory devices
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A system and method for obtaining ECG signals from an ambulatory patient are disclosed herein. The system is configured to be inexpensive, small, and robust for outpatient monitoring. The system is configured to be a low power consuming device. The system provides options for a variety of settings and real-time access to the ECG signals being recorded during the recording period.

Claims

1. A portable electrocardiogram (ECG) recorder, comprising:

a first memory included in a first integrated circuit (IC) chip;

a microcontroller included in a second IC chip; and

a second memory included in a third IC chip, wherein the microcontroller is configured to communicate with each of the first memory and the second memory, the microcontroller is configured to turn on in accordance with a capacity state of the first memory, and the second memory is configured to turn on in accordance with a control signal from the microcontroller.

2. The recorder of claim 1, wherein the first memory comprises a first-in-first-out (FIFO) memory.

3. The recorder of claim 1, wherein the microcontroller comprises a microprocessor or microcomputer.

4. The recorder of claim 1, wherein the second memory comprises a flash memory.

5. The recorder of claim 1, wherein ECG data obtained from a patient are temporarily stored in the first memory and then stored long-term in the second memory.

6. The recorder of claim 1, wherein the microcontroller is turned off when ECG data stored in the first memory has been transferred to the second memory.

7. The recorder of claim 1, wherein the microcontroller is turned on for a time period on the order of approximately 500 μ

s per duty cycle.

8. The recorder of claim 1, wherein the second memory is turned on for a time period on the order of approximately 200 μ

s per duty cycle.

9. The recorder of claim 1, wherein the control signal is transmitted from the microcontroller to the second memory when the microcontroller has received ECG data from the first memory and has determined write-to locations of the received ECG data to the second memory.

10. The recorder of claim 1, wherein the microcontroller is configured to store a sampling rate specified during initiation of the recorder, and a duty cycle of the microcontroller is determined as a function of the stored sampling rate.

11. The recorder of claim 1, wherein each of the microcontroller and second memory is actuated for less than approximately 5% of a duty cycle.

12. A method for low power operation of an electrocardiogram (ECG) recorder, the method comprising:

actuating a microcontroller for a first time period sufficient to write ECG data from a first-in-first-out (FIFO) memory to a flash memory; and

actuating the flash memory for a second time period sufficient to accept the ECG data, wherein the first and second time periods substantially coincide with each other, and the second time period is shorter than the first time period.

13. The method of claim 12, comprising:

storing the ECG data obtained from a patient in the FIFO memory; and

transmitting an actuation signal to the microcontroller when the FIFO memory is approximately at full capacity.

14. The method of claim 12, wherein actuating the flash memory includes the microcontroller actuating the flash memory.

15. The method of claim 12, comprising:

powering off the microcontroller and flash memory for remainder of the duty cycle; and

acquiring ECG data throughout the duty cycle.

16. The method of claim 12, wherein actuating the microcontroller includes a power consumption on the order of approximately 20 milliamp per duty cycle.

17. The method of claim 12, wherein actuating the flash memory includes a power consumption on the order of approximately 30 milliamp per duty cycle.

18. Circuitry for an electrocardiogram (ECG) monitor, comprising:

means for temporarily storing ECG signals continuously obtained from a patient;

means for transferring the ECG signals; and

means for storing the ECG signals, wherein the means for transferring is powered for a minimum time period sufficient to control transfer of the ECG signals from the means for temporarily storing to the means for storing, the means for transferring powered on in accordance with a capacity state of the means for temporarily storing, and the means for storing actuated by the means for transferring.

19. The circuitry of claim 18, wherein the means for transferring and means for storing are intermittently powered for the minimum time period necessary to transfer the ECG signals each time the means for temporarily storing is at or approaching full capacity.

20. The circuitry of claim 18, wherein each of the means for temporarily storing, means for transferring, and means for storing is provided on a separate integrated circuit (IC) chip.

21. The circuitry of claim 18, wherein the means for transferring is turned off when the ECG signals have been written to the means for storing.

22. The circuitry of claim 18, wherein the means for storing is turned off by the means for transferring upon completion of a write operation of the ECG signals.

23. The circuitry of claim 18, wherein the means for temporarily storing comprises a first-in-first-out (FIFO) memory.

24. The circuitry of claim 18, wherein the means for transferring comprises a microprocessor.

25. The circuitry of claim 18, wherein the means for storing comprises a RAM memory.

26. The circuitry of claim 18, wherein the capacity state is at least one of a full capacity indication or near-full capacity indication.

27. The circuitry of claim 18, wherein the means for transferring is turned on for a longer period of time than the means for storing.

28. The circuitry of claim 18, wherein the ECG signals include a multi-channel ECG data, notation data, and error check data.

29. The circuitry of claim 18, comprising a decimation filter coupled to the input of the means for temporarily storing.