Method and system for receiver detection in PCI-Express devices

• US 20060230211A1
• Filed: 04/06/2005
• Published: 10/12/2006
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Woodral, David E.
• Granted Patent: US 7,231,480 B2
• Time in Patent Office: Days
• US Class Current: 710/302
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A method and system for detecting when a receiver in a host system is present or absent to receive information from a PCI-Express device is provided. The method includes monitoring a signal received from a serial/de-serializer for transitions; re-starting a first timer when a transition is detected; and detecting a receiver'"'"'s absence if a second timer has reached a maximum value after a transition is detected and a first timer cycle is incomplete. The PCI-Express device includes a receiver detection logic that determines when a receiver is absent before sending any data to the host system. The PCI-Express device may be a host adapter.

Claims

1. A method for detecting when a receiver in a PCI-Express device is present or absent to receive information, comprising:

monitoring a signal received from a serial/de-serializer for transitions;

re-starting a first timer when a transition is detected; and

detecting a receiver'"'"'s absence if a second timer has reached a maximum value after a transition is detected and a first timer cycle is incomplete.

2. The method of claim 1, wherein a first timer output value is compared to a programmed value and if the first timer output value is equal to the programmed value then a receiver is presumed to be present.

3. The method of claim 1, wherein a second timer output value is compared to a programmed value and when the second timer output value is not equal to the programmed value, a signal is produced to declare a receiver'"'"'s absence.

4. The method of claim 3, wherein if the second timer output value is equal to the programmed value, then a receiver is presumed to be present.

5. The method of claim 1, wherein if a transition is not detected then an edge detector continues to monitor the signal received from the serial/de-serializer.

6. The method of claim 1, wherein if a transition is not detected, then a receiver is presumed to be present.

7. The method of claim 1, wherein an output control module generates a signal to declare if a receiver is present or absent.

8. The method of claim 1, wherein the PCI-Express device is a host bus adapter.

9. A PCI-Express device, comprising:

receiver detection logic that determines when a receiver is absent before sending any data to another PCI-Express device.

10. The PCI-Express device of claim 9, wherein an edge detector module monitors a signal received from a serial de-serializer for any transitions.

11. The PCI-Express device of claim 9, wherein if a transition is detected, a first timer is re-started.

12. The PCI-Express device of claim 11, wherein a second timer is used to declare that a receiver is absent when the first timer'"'"'s cycle is incomplete after a certain time interval.

13. The PCI-Express device of claim 12, wherein the time interval is programmable.

14. The PCI-Express device of claim 12, wherein an output control module receives an input based on a comparison of a second timer value and a programmed value and declares that a receiver is absent.

15. The PCI-Express device of claim 11, wherein if an output from the first timer is equal to a programmed value, then a receiver is presumed to be present.

16. The PCI-Express device of claim 9, wherein the PCI-Express device is a host bus adapter.

17. A system for connecting host systems with storage devices comprising:

a PCI-Express device with a receiver detection logic that determines when a receiver is absent before sending any data to a host system.

18. The system of claim 17, wherein an edge detector module monitors a signal received from a serial de-serializer for any transitions.

19. The system of claim 17, wherein if a transition is detected, a first timer is re-started.

20. The system of claim 19, wherein a second timer is used to declare that a receiver is absent when the first timer'"'"'s cycle is incomplete after a certain time interval.

21. The system of claim 19, wherein the time interval is programmable.

22. The system of claim 19, wherein an output control module receives an input based on a comparison of a second timer value and a programmed value and declares that a receiver is absent.

23. The system of claim 19, wherein if an output from the first timer is equal to a programmed value, then a receiver is presumed to be present.

24. The system of claim 17, wherein the PCI-Express device is a host bus adapter.