Systems and methods for CPU repair
First Claim
Patent Images
1. A method of repairing a processor comprising the steps of:
- assigning each cache element a quality rank based on each cache element'"'"'s error rate;
comparing the quality rank of an allocated cache element to the quality rank of a non-allocated cache element; and
swapping in said non-allocated cache element for said allocated cache element based on said comparison.
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Accused Products
Abstract
In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
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Citations
38 Claims
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1. A method of repairing a processor comprising the steps of:
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assigning each cache element a quality rank based on each cache element'"'"'s error rate;
comparing the quality rank of an allocated cache element to the quality rank of a non-allocated cache element; and
swapping in said non-allocated cache element for said allocated cache element based on said comparison. - View Dependent Claims (2, 35, 36)
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3. A method of repairing a processor comprising the steps of:
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assigning each cache element a severity rank based on each cache element'"'"'s error rate;
comparing the severity rank of an allocated cache element to the severity rank of a non-allocated cache element; and
swapping in said non-allocated cache element for said allocated cache element based on said comparison. - View Dependent Claims (4)
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5. A CPU cache element management system comprising:
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at least one processor having at least one allocated cache element and at least one non-allocated cache element;
a cache management logic operable to assign said allocated cache element and said non-allocated cache element a quality rank, operable to compare the quality rank of said allocated cache element to the quality rank of said non-allocated cache element, and operable to swap in said non-allocated cache element for said allocated cache element based on said comparison. - View Dependent Claims (6, 7, 8, 9, 11, 13, 14, 16, 18, 37)
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10. A CPU cache element management system comprising:
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at least one processor having at least one allocated cache element and at least one non-allocated cache element;
a cache managing logic operable to assign said allocated cache element and said non-allocated cache element a severity rank, operable to compare the severity rank of said allocated cache element to the severity rank of said non-allocated cache element, and operable to swap in said non-allocated cache element for said allocated cache element based on said comparison. - View Dependent Claims (12, 38)
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15. A computer system comprising:
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at least one processor having at least one allocated cache element and at least one non-allocated cache element; and
a cache managing logic operable to assign said allocated cache element and said non-allocated cache element a quality rank, operable to compare the quality rank of said allocated cache element to the quality rank of said non-allocated cache element, and operable to swap in said non-allocated cache element for said allocated cache element if the quality rank of said non-allocated cache element is lower than the quality rank of said allocated cache element.
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17. A computer system comprising:
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at least one processor having at least one allocated cache element and at least one non-allocated cache element;
a cache managing logic operable to assign said allocated cache element and said non-allocated cache element a severity rank, operable to compare the severity rank of said allocated cache element to the severity rank of said non-allocated cache element, and operable to swap in said non-allocated cache element for said allocated cache element if the severity rank of said non-allocated cache element is lower than the severity rank of said allocated cache element.
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19. A method for repairing a computer system having an operating system comprising the steps of:
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monitoring at least one allocated cache element associated with at least one CPU for at least one cache error;
recording cache error information associated with said at least one cache error;
updating a cache error history database with said logged cache error information;
evaluating said cache error history database to determine a quality rank for said allocated cache element;
assigning said quality rank to said allocated cache element corresponding to a total number of errors occurring in said cache element over a predetermined time period;
determining that said allocated cache element is faulty based on said quality rank of said allocated cache element;
comparing the quality rank of said faulty allocated cache element to a quality rank of a non-allocated cache element; and
swapping in said non-allocated cache element for said faulty cache element if the quality rank of said non-allocated cache element is less than the quality rank of said faulty cache element. - View Dependent Claims (20)
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21. A method for managing a computer system comprising the steps of:
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monitoring at least one allocated cache element associated with at least one CPU for at least one cache error;
recording cache error information associated with said at least one cache error;
updating a cache error history database with said logged cache error information;
evaluating said cache error history database to determine a severity rank for said allocated cache element;
assigning said severity rank to said allocated cache element;
determining that said cache element is faulty based on said severity rank of said allocated cache element;
comparing the severity rank of said faulty allocated cache element to a severity rank of a non-allocated cache element;
swapping in said non-allocated cache element for said faulty allocated cache element if the severity rank of said non-allocated cache element is less than the severity rank of said faulty allocated cache element. - View Dependent Claims (22)
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23. A processor comprising:
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a plurality of first memory portions;
a plurality of second memory portions;
logic for determining whether a first memory portion is faulty; and
logic for replacing the faulty first memory portion with a second memory portion if said first memory portion has a worse quality rank than said second memory portion. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A processor comprising:
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a first cache means configured for high-speed information storage and retrieval from the processor;
a second cache means for high-speed information storage and retrieval;
means for determining whether any portion of the first cache means configured for high-speed information storage is faulty; and
means for replacing the faulty portion of the first cache means with at least a portion of the second cache means for high-speed information storage and retrieval if said first cache means has a worse quality rank than said second cache means. - View Dependent Claims (30, 31, 32, 33, 34)
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Specification