Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications

• US 20060231882A1
• Filed: 03/28/2006
• Published: 10/19/2006
• Est. Priority Date: 03/28/2005
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Tuller, Harry L., Kim, Il-Doo
• Granted Patent: US 7,544,967 B2
• Time in Patent Office: Days
• US Class Current: 257/310
• CPC Class Codes: G01N 27/4141 specially adapted for gases
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02269 deposition by thermal evaporation H01L21/02293 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/472 the gate dielectric comprising only inorganic materials
• CPC Class Codes: H10K 10/474 the gate dielectric comprising a multilayered structure
• CPC Class Codes: H10K 30/65 Light-sensitive field-effect devices, e.g. phototransistors
• CPC Class Codes: H10K 39/30 Devices controlled by radiation
• CPC Class Codes: H10K 77/111 Flexible substrates
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
• CPC Class Codes: Y02E 10/549 Organic PV cells

Abstract

A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

Claims

1. A low voltage operating thin film transistor (TFT) structure comprising:

a source electrode;

a drain electrode;

a gate electrode; and

a gate insulator that is coupled to said source electrode, drain electrode, and gate electrode, said gate insulator including room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

2. The TFT structure of claim 1 further comprising a plastic substrate such as PET, PEN, PES, or polyimide that is supported said gate electrode.

3. The TFT structure of claim 1 further comprising a semiconductor layer that is coupled to said source, drain electrode and said gate insulator.

4. The TFT structure of claim 2, wherein said semiconductor layer comprises pentacene, poly-3-alkykthiophene, poly-3-hexylthiophene (P3HT), poly-thienlylene vinylene or tetracene.

5. The TFT structure of claim 2, wherein said semiconductor layer comprises ZnO, In₂O₃, TiO₂, or SnO₂.

6. The TFT structure of claim 2, wherein the semiconductor layer is deposited at room temperature by RF magnetron sputtering.

7. The TFT structure of claim 1, wherein said gate insulator comprises at least one material selected from the group consisting of Bi₂(Zn_1/3Nb_2/3)₂O₇, Bi_1.5Zn_1.0M_1.5O₇ (M=Nb, Ta, Sb), or 0.1˜

5% Ni, Mg, or Mn doped (Ba<sub>1−

x</sub>Sr_x)TiO₃ which is deposited at room temperature to make amorphous or partially nanocrystalline films by RF magnetron sputtering.

8. The TFT structure of claim 1, wherein the high-K insulator layer comprising room temperature RF sputtered inorganic films such as very thin (0.1 nm−

30 nm) MgO, YSZ (yttrium-stabilized zirconia), CeO₂, Y₂O₃, Al₂O₃, HfO₂, SrTiO₃, LaAlO₃, MgAl₂O₄ deposited on the high-K films to manipulate threshold voltage to fabricate enhancement or depletion mode TFTs for use in CMOS application.

9. The TFT structure of claim 1, wherein said gate electrode comprises a catalyst metal.

10. The TFT structure of claim 9, wherein said catalyst metal comprises Poly-Si, Al, Cr, Ni, Pt, Pd, Au, ITO, TiN, or W.

11. The TFT structure of claim 9, wherein said gate electrode is formed in a region interior of said gate dielectric.

12. The TFT structure of claim 9, wherein said gate electrode is formed in a region exterior of said gate dielectric.

13. A method of forming a thin film transistor (TFT) structure comprising:

forming a source electrode;

forming a drain electrode;

forming a gate electrode; and

forming a gate insulator that is coupled to source electrode, drain electrode, and gate electrode, said gate insulator including room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltages.

14. The method of claim 13 further comprising providing a plastic substrate such as PET, PEN, PES, or polyimide that is supported by said gate electrode.

15. The method of claim 13, wherein said gate insulator comprises at least one material selected from the group consisting of Bi₂(Zn_1/3Nb_2/3)₂O₇, Bi_1.5Zn_1.0M_1.5O₇ (M=Nb, Ta, Sb), or 0.1−

5% Ni, Mg, or Mn doped (Ba<sub>1−

x</sub>Sr_x)TiO₃ which is deposited at room temperature to make amorphous or partially nanocrystalline films by RF magnetron sputtering.

16. The method of claim 13 further comprising forming a semiconductor layer that is coupled to said source, drain electrode and said gate insulator.

17. The method of claim 16, wherein said semiconductor layer comprises pentacene, poly-3-alkykthiophene, poly-3-hexylthiophene (P3HT), poly-thienlylene vinylene or tetracene.

18. The method of claim 16, wherein said semiconductor layer comprises ZnO, In₁₋

xGa_xZnO (IGZO), or SnO₂.

19. The method of claim 13, wherein said gate electrode comprises a catalyst metal.

20. The method of claim 19, wherein said catalyst metal comprises Poly-Si, Al, Cr, Ni, Pt, Pd, Au, ITO, TiN, or W.

21. The method of claim 19, wherein said gate electrode is formed in a region interior of said gate dielectric.

22. The method of claim 19, wherein said gate electrode is formed in a region exterior of said gate dielectric.