Robust leaded molded packages and methods for forming the same

• US 20060231933A1
• Filed: 06/01/2006
• Published: 10/19/2006
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Elsie Agdon Cabahug, Lilith U. Montayre, Margie S. Tumulak-Rios, Marvin R. Gestole, Romel N. Manatad
• Inventors: Tumulak-Rios, Margie S., Manatad, Romel N., Montayre, Lilith U., Cabahug, Elsie Agdon, Gestole, Marvin R.
• Granted Patent: US 7,560,311 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

Claims

1-9. -9. (canceled)

10. A semiconductor package comprising:

(a) a semiconductor die including a first side and a second side;

(b) a leadframe structure comprising (i) a die attach region comprising an aperture that passes through the die attach region, and (ii) a plurality of leads extending away from the die attach region;

(c) a plurality of solder structures between the semiconductor die and the leadframe structure and coupling the die attach region to the semiconductor die;

(d) a depression in the leadframe structure, the depression being between the one of the solder structures in the plurality of leadframe structures, and one of the leads in the plurality of leads; and

(e) a molding material covering the die attach region of the leadframe structure, the plurality of solder structures, and the first side of the semiconductor die, and wherein the molding material is also within the aperture of the die attach region.

11. The semiconductor package of claim 10, wherein an exterior surface molding material is substantially co-planar with the second side of the semiconductor die.

12. The semiconductor package of claim 10, wherein the solder structure comprises a high lead solder bump and a solder deposit.

13. The semiconductor package of claim 10, wherein the leadframe structure comprises a layer of metal plating.

14. The semiconductor package of claim 10 wherein ends of the plurality of leads are substantially coplanar with an exterior surface of molding material and the second side of the semiconductor die.

15. The semiconductor package of claim 10 further comprising a plurality of depressions, the depressions being respectively located proximate to inner portions of the leads.

16. The semiconductor package of claim 10, wherein the semiconductor die comprises a power MOSFET.

17. The semiconductor package of claim 10 wherein the semiconductor die comprises a bond pad at the first side, wherein the bond pad comprises an uneven surface.

18. The semiconductor package of claim 17 wherein the uneven surface comprises a scalloped surface.

19. The semiconductor package of claim 10 wherein the molding material comprises an epoxy molding material.

20. A semiconductor package comprising:

(a) a semiconductor die including a first side and a second side, wherein the semiconductor die further includes a bond pad at the first side, the bond pad comprising an uneven surface;

(b) a leadframe structure comprising (i) a die attach region and an aperture in the die attach region, and (ii) a plurality of leads extending away from the die attach region;

(c) a plurality of solder structures between the semiconductor die and the leadframe structure and coupling the die attach region to the semiconductor die; and

(d) a molding material covering the die attach region of the leadframe structure, the solder structure, and the first side of the semiconductor die, and wherein the molding material is also within the aperture.

21. The semiconductor package of claim 20 wherein the uneven surface comprises a scalloped surface.

22. The semiconductor package of claim 20 wherein an exterior surface molding material is substantially co-planar the second side of the semiconductor die.

23. The semiconductor package of claim 20 wherein each solder structure in the plurality of solder structures comprises a high lead solder bump and a solder deposit.

24. The semiconductor package of claim 20 wherein the leadframe structure comprises a layer of metal plating.

25. The semiconductor package of claim 20 further comprising a plurality of depressions, the depressions being located proximate to inner portions of the leads.

26. The semiconductor package of claim 20 wherein the molding material comprises an epoxy molding material.

27. The semiconductor package of claim 20 wherein the semiconductor die comprises a power MOSFET.

28. The semiconductor package of claim 20 wherein an exterior surface of the molded molding material is substantially co-planar with the second side of the semiconductor die, and wherein the semiconductor die comprises a power MOSFET having a gate region and a source region at the first side, and a drain region at the second side.

29. The semiconductor package of claim 20 wherein an exterior surface molding material is substantially co-planar with the second side of the semiconductor die, and wherein the semiconductor die comprises a power MOSFET having a gate region and a source region at the first side, and a drain region at the second side, and wherein the leadframe further comprises a plurality of depressions, the depressions being located proximate to inner portions of the leads.

30. A method for forming a semiconductor package, the method comprising:

(a) providing a plurality of leadframe structures in a leadframe carrier comprising a saw guide slot, wherein the leadframe carrier comprises a plurality of leadframe structures, each leadframe structure comprising (i) a die attach region, and (ii) a plurality of leads extending away from the die attach region;

(b) attaching semiconductor dies to the die attach regions, wherein a plurality of solder structures is between each semiconductor die and each die attach region;

(c) molding a molding material around at least a portion of each semiconductor die and at least a portion of each die attach region; and

(d) cutting the leadframe carrier with a saw using the saw guide slot.

31. The method of claim 30 wherein the leadframe carrier is on a jig including vacuum holes.

32. The method of claim 30 further comprising depositing solder paste on the die attach regions, and wherein each of the semiconductor dies is bumped with high lead solder bumps.

33. The method of claim 30 wherein each semiconductor die comprises a first side and a second side, and wherein after (d), the molded molding material covers the first side of the semiconductor die and exposes the second side of the semiconductor die.

34. The method of claim 30 wherein each of the plurality of leadframe structures comprises a layer of metal plating.

35. The method of claim 30 further comprising forming a solder deposit on each of the die attach regions of the leadframe structures after (a) and before (b).

36. The method of claim 30 wherein the molding material comprises an epoxy molding compound.

37. The method of claim 30 wherein (d) molding comprises using a film assisted molding process.

38. The method of claim 30 wherein each leadframe structure includes a plurality of depressions, each depression being between a die attach region and a lead.

39. The method of claim 30 wherein each die attach region of each leadframe structure comprises a slot.

40. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region comprising an aperture, and (ii) a plurality of leads extending away from the die attach region;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, and a bond pad having an uneven surface at the first side, and wherein a plurality of solder structures is between the semiconductor die and the die attach region;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region, wherein the molding material passes through the aperture in the die attach region.

41. The method of claim 40 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

42. The method of claim 40 wherein the semiconductor die comprises a vertical transistor.

43. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region comprising an aperture, (ii) a plurality of leads extending away from the die attach region, and (iii) a plurality of depressions, each depression being proximate to an inner portion of a lead;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, and a bond pad at the first side, and wherein a plurality of solder structures is between the semiconductor die and the die attach region;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region, wherein the molding material passes through the aperture in the die attach region.

44. The method of claim 43 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

45. The method of claim 43 wherein the semiconductor die comprises a vertical transistor.

46. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region, (ii) a plurality of leads extending away from the die attach region, and (iii) a plurality of depressions, each depression being proximate to an inner portion of a lead in the plurality of leads;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, and a bond pad having an uneven surface at the first side, and wherein a plurality of solder structures is between the semiconductor die and the die attach region;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region.

47. The method of claim 46 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

48. The method of claim 46 wherein the semiconductor die comprises a vertical transistor.