Bonding pad for a packaged integrated circuit

• US 20060231959A1
• Filed: 03/17/2006
• Published: 10/19/2006
• Est. Priority Date: 07/07/2003
• Status: Abandoned Application

• Current Assignee: Fuaida Harun, Lan Chu Tan, Liang Jen Koh
• Original Assignee: Fuaida Harun, Lan Chu Tan, Liang Jen Koh
• Inventors: Tan, Lan Chu, Harun, Fuaida, Koh, Liang Jen
• Application Number:
  US11/377,996
• Publication Number:
  US 20060231959A1
• Time in Patent Office: Days
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45164 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/4917 Crossed wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.

Claims

1-18. -18. (canceled)

19. A package substrate for an integrated circuit, comprising:

a top traceless surface;

a bottom traceless surface;

a plurality of vias in the package substrate extending between the top and bottom traceless surfaces;

a plurality of via capture pads arranged on the top traceless surface, wherein each of the via capture pads surrounds a respective one of the vias and each via capture pad includes;

a land area;

a clearance area surrounding the land area; and

a photo mask surrounding the clearance area; and

wherein each via capture pad includes at least one sharp edge that assists a pattern recognition system of a wire bonder in locating at least one bond wire on the via capture pad.

20. The package substrate of claim 19, wherein the integrated circuit is electrically coupled to the plurality of vias using a plurality of traceless conductors.

21. The package substrate of claim 20, wherein the plurality of traceless conductors comprises a plurality of insulated wires.

22. The package substrate of claim 19, wherein the package substrate is a ball grid array (BGA) substrate.

24. The package substrate of claim 19, wherein each clearance area comprises BT.

26. The package substrate of claim 19, further comprising a plurality of plugs located in respective ones of the plurality of vias.

27. The package substrate of claim 19, wherein all of the via capture pads are rectangular shaped and have varying numbers of cut-outs therein.

28. The package substrate of claim 19, wherein each land area comprises a conductive metal.

29. The package substrate of claim 28, wherein the conductive metal comprises one of copper, gold, silver and aluminum.

30. The package substrate of claim 19, wherein the vias are arranged in an array.

23. (canceled)

25. (canceled)