Dither amplitude correction for constant current drivers
First Claim
1. A switched driver circuit for generating a switched drive signal including a dither waveform, the switched driver circuit comprising:
- a dither generator circuit having a clock input and being configured to generate a dither signal based on the clock input;
a gate control circuit configured to generate the switched drive signal based on the dither signal;
a dither correction circuit being configured to suspend the dither signal based on a signal parameter of the switched drive signal.
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Accused Products
Abstract
In satisfying the above need, as well as overcoming the enumerated drawbacks and other limitations of the related art, the present invention provides an improved switched driver circuit. As disclosed above, there is a need to compensate for the high impedance load characteristics in certain implementations of hysteretic switching constant current drivers. The switching waveform of switching constant current driver circuits may be modified in such a way that retains the important dither characteristics and improves system level performance.
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Citations
18 Claims
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1. A switched driver circuit for generating a switched drive signal
including a dither waveform, the switched driver circuit comprising: -
a dither generator circuit having a clock input and being configured to generate a dither signal based on the clock input;
a gate control circuit configured to generate the switched drive signal based on the dither signal;
a dither correction circuit being configured to suspend the dither signal based on a signal parameter of the switched drive signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A switched driver circuit for generating a switched drive signal including a dither waveform, the switched driver circuit comprising:
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a dither generator circuit having a clock input and being configured to generate a dither signal based on the clock input;
a first comparator in electrical communication with the dither generator circuit and configured to generate an upper threshold signal based on the dither signal;
a second comparator in electrical communication with the dither generator circuit and configured to generate a lower threshold signal based on the dither signal;
a gate control circuit in electrical communication with the first and second comparator to receive the upper and lower threshold signal, the gate control circuit being configured to generate the switched drive signal;
a dither correction circuit in electrical communication with the first and second comparator to receive the upper and lower threshold signal, the dither correction circuit being configured to suspend the dither signal when the upper or lower threshold signal is not received within a first predefined time period. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification