Semiconductor integrated circuit

• US 20060232320A1
• Filed: 04/13/2006
• Published: 10/19/2006
• Est. Priority Date: 04/14/2005
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Seki, Hiroshi, Tokiwai, Hiroshi, Kakubari, Hideyuki
• Granted Patent: US 7,656,210 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.

Claims

1. A semiconductor integrated circuit operating on multiple supply potentials including a first potential and a second potential that is higher than the first potential, comprising:

a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof;

a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level; and

a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.

2. The semiconductor integrated circuit according to claim 1, wherein the potential-lowering circuit comprises multiple N-channel MOS transistors whose drain-source paths are series-connected and whose gates are applied with the second supply potential.

3. The semiconductor integrated circuit according to claim 1, wherein the potential-lowering circuit is constituted by series-connecting multiple N-channel MOS transistors that are saturation-connected.

4. The semiconductor integrated circuit according to claim 1, wherein the judging circuit comprises:

a first inverter that receives and inverts the first supply potential;

multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter; and

a second inverter that inverts a signal outputted from the first inverter, wherein;

a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to a ground potential.

5. The semiconductor integrated circuit according to claim 1, wherein the judging circuit includes:

a first inverter that receives and inverts the first supply potential;

multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter; and

a second inverter that inverts a signal outputted from the first inverter, wherein;

a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to the first supply potential.

6. The semiconductor integrated circuit according to claim 4, wherein:

the first inverter includes multiple P-channel MOS transistors whose drain-source paths are series-connected and whose gates are applied with the first supply potential; and

the second inverter includes multiple P-channel MOS transistors whose source-drain paths are series-connected and whose gates are applied with signals outputted from the first inverter.

7. The semiconductor integrated circuit according to claim 1, wherein:

the buffer circuit includes multiple inverters and outputs a differential signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.

8. The semiconductor integrated circuit according to claim 1, further comprising:

an internal circuit that operates on the first supply potential;

a first level-shifter and a second level-shifter that shift a potential of a signal outputted from the internal circuit;

an output driver including a P-channel MOS transistor and an N-channel MOS transistor that are series-connected to generate an output signal based on a signal outputted from the first level-shifter and the second level-shifter, respectively, if the second supply potential is fed; and

a switching circuit that fixes a gate potential of the P-channel MOS transistor at a high level and a gate potential of the N-channel MOS transistor at a low level based on the control signal outputted from the buffer circuit.