Circuit and method for stable fuse detection
First Claim
1. A fuse state detection circuit, comprising:
- a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.
8 Assignments
0 Petitions
Accused Products
Abstract
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal that whose state is recoverable from to a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.
22 Citations
52 Claims
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1. A fuse state detection circuit, comprising:
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a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown. - View Dependent Claims (2, 3, 4)
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5. A fuse state detection circuit, comprising:
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a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event. - View Dependent Claims (6, 7, 8, 9)
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10. A fuse state detection circuit, comprising:
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a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse. - View Dependent Claims (11, 12, 13, 14)
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- 15. A method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting.
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20. A method of operating a fuse state detection circuit, comprising:
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monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.
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21. A method of operating a fuse state detection circuit, comprising:
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monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that is responsive to the states of said first and said second fuse elements and whose state is resistant to a negative triggering event. - View Dependent Claims (22)
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23. A method of operating a fuse state detection circuit, comprising:
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monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that is responsive to the states of said first and said second fuse elements and resolves itself to the correct state without the need for a reset pulse. - View Dependent Claims (24)
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25. A memory device, comprising:
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an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown. - View Dependent Claims (26, 27, 28)
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29. A memory device, comprising:
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an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event. - View Dependent Claims (30, 31, 32, 33)
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34. A memory device, comprising:
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an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse. - View Dependent Claims (35, 36, 37, 38)
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39. A system, comprising:
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a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising;
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown. - View Dependent Claims (40, 41, 42)
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43. A system, comprising:
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a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising;
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event. - View Dependent Claims (44, 45, 46, 47)
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48. A system, comprising:
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a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising;
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising;
a fuse state detection circuit, comprising;
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse. - View Dependent Claims (49, 50, 51, 52)
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Specification