Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction

• US 20060232590A1
• Filed: 01/25/2006
• Published: 10/19/2006
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Remez, Offir, Fogel, Efi
• Granted Patent: US 7,812,844 B2
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A high performance graphics processing and display system architecture realized on a monolithic silicon chip, supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.

Claims

1. A silicon chip of a monolithic construction implementing a graphics processing and display system having multiple GPU-driven pipeline cores each with graphic processing u that support the parallelization of image processing using one or more parallelization modes, and being adapted for interfacing with a computing system having a means for displaying images on at least one computer screen and supporting (i) one or more software applications for issuing graphics commands, (ii) one or more graphic libraries (i.e. OpenGL and DirectX—

state machines for storing data used to implement said graphics commands, and (iii) multi-pipe drivers for allowing said GPU-drive pipeline cores to interact with said graphic libraries, wherein said multi-pipe drivers include (1) a GPU drivers unit for performing the functions of a generic GPU driver associated with interaction with the operating system (OS) of said computing system, and graphic library (e.g. OpenGL or DirectX), (2) a distributed graphic functions control module for performing functions associated with carrying on the different parallelization modes according to parallelization policy management, (3) a state monitoring driver module for continuously analysis of all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphic pipeline cores, (4) an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said computing system for identifying problem areas within said graphics system which are likely to cause data bottlenecks, wherein said application profiling and analysis driver modules uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, (ii) registers of said control unit, and graphic API commands, and (5) parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by means of the control unit of MP-SOC.

said silicon chip comprising;

said multiple GPU-driven pipeline cores;

a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit,

wherein the way said data is distributed is dictated by said control unit, and depending on the current parallelization mode;

a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;

a control unit, for controlling the configuration and functioning of said graphics processing and display system according to the selected parallelization mode;

a processing element (PE) with internal or external memory;

a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and

a display interface, for running single or multiple display screens.

2. The silicon chip of claim 1, further comprises cache memory, for serving said processing element, and for caching graphics data common to said GPU-driven pipeline cores.

3. The silicon chip of claim 2, wherein said graphics data is selected from the group consisting of textures and vertex objects.

4. The silicon chip of claim 1, wherein said benchmarking data include data selected from the group consisting of memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among graphic pipelines, volumes of transferred data, textures count, and depth complexity.

5. The silicon chip of claim 1, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

6. The silicon chip of claim 1, wherein the number of said GPU-driven pipeline cores has no architectural limit.

7. The silicon chip of claim 1, wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

8. The silicon chip of claim 7, wherein said parallelization modes include an object division mode, an image division mode and a time division mode.

9. The silicon chip of claim 1, wherein said benchmarking data includes memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among pipeline cores, volumes of transferred data, textures count, and depth complexity.

10. The silicon chip of claim 1, realized on a graphics card which can be connected to the motherboard of said computing system.

17. The graphics card of claim 4, wherein said benchmark parameters include data selected from the group consisting of memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among graphic pipelines, volumes of transferred data, textures count, and depth complexity.

11. A graphics card for connection to the motherboard of a computing system having a CPU bus, said graphics card comprising:

a silicon chip of a monolithic construction implementing a graphics processing and display subsystem including;

(a) multiple GPU-driven pipeline cores;

(b) a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit;

(c) a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;

(d) a control unit, for controlling the configuring and functioning of said graphics processing and display system according to the parallelization mode selected at any instant in time;

(d) a processing element (PE) with internal or external memory;

(e) a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and

(f) a display interface, for running single or multiple display screens.

12. The graphics card of claim 11, wherein said graphics data stream is distributed among said GPU-driven pipeline cores, under the control of said control unit, and depending on the current parallelization mode.

13. The graphics card of claim 11, wherein said silicon chip has multiple GPU-driven pipeline cores each with graphic processing unit (GPU) that supports the parallelization of image processing using one or more parallelization modes, and being adapted for interfacing with a computing system having a means for displaying images on at least one computer screen and supporting (i) one or more software applications for issuing graphics commands, (ii) one or more graphic libraries (state machines) for storing data used to implement said graphics commands, and (iii) multi-pipe drivers for allowing said GPU-drive pipeline cores to interact with said graphic libraries.

14. The graphics card of claim 12, wherein said multi-pipe drivers include:

(1) a GPU drivers unit for performing the functions of a generic GPU driver associated with interaction with the operating system (OS) of said computing system, and graphic library;

(2) a distributed graphic functions control module for performing functions associated with carrying on the different parallelization modes according to parallelization policy management;

(3) a state monitoring driver module for continuously analysis of all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphic pipeline cores;

(4) an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said computing system identifying problem areas within said graphics system which are likely to cause data bottlenecks, wherein said application profiling and analysis driver modules uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, (ii) registers of said control unit, and graphic API commands; and

(5) parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by means of the control unit of MP-SOC.

15. The graphics card of claim 11, further comprises cache memory, for serving said processing element, and for caching graphics data common to said GPU-driven pipeline cores.

16. The graphics card of claim 15, wherein said graphics data is selected from the group consisting of textures and vertex objects.

18. The graphics card of claim 11, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

19. The graphics card of claim 11, wherein the number of said GPU-driven pipeline cores has no architectural limit.

20. The graphics card of claim 11, wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

21. The graphics card of claim 11, wherein said parallelization modes include an object division mode, an image division mode and a time division mode.

22. A computer system for display images on more or more display screens, comprising:

a motherboard having a CPU bus and a silicon chip of a monolithic construction for implementing a graphics processing and display subsystem, said silicon chip including;

(a) multiple GPU-driven pipeline cores;

(b) a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit,

wherein the way said data is distributed is dictated by said control unit, and depending on the current parallelization mode;

a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;

a control unit, for controlling the configuring and functioning of said graphics processing and display system according to the parallelization mode selected at any instant in time;

a processing element (PE) with internal or external memory;

a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and

a display interface, for running single or multiple display screens.

23. The computer system of claim 22, wherein said graphics data stream is distributed among said GPU-driven pipeline cores, under the control of said control unit, and depending on the current parallelization mode.

24. The computer system of claim 22, wherein said silicon chip has multiple GPU-driven pipeline cores each with graphic processing unit (GPU) that supports the parallelization of image processing using one or more parallelization modes, and being adapted for interfacing with a computing system having a means for displaying images on at least one computer screen and supporting (i) one or more software applications for issuing graphics commands, (ii) one or more graphic libraries (state machines) for storing data used to implement said graphics commands, and (iii) multi-pipe drivers for allowing said GPU-drive pipeline cores to interact with said graphic libraries.

25. The computer system of claim 24, wherein said multi-pipe drivers comprises:

(1) a GPU drivers unit for performing the functions of a generic GPU driver associated with interaction with the operating system (OS) of said computing system, and graphic library;

(2) a distributed graphic functions control module for performing functions associated with carrying on the different parallelization modes according to parallelization policy management;

(3) a state monitoring driver module for continuously analysis of all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphic pipeline cores;

(4) an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said computing system identifying problem areas within said graphics system which are likely to cause data bottlenecks, wherein said application profiling and analysis driver modules uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, (ii) registers of said control unit, and graphic API commands; and

(5) parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by means of the control unit of MP-SOC.

26. The computer system of claim 22, further comprises cache memory, for serving said processing element, and for caching graphics data common to said GPU-driven pipeline cores.

27. The computer system of claim 22, wherein said graphics data is selected from the group consisting of textures and vertex objects.

28. The computer system of claim 22, wherein said benchmark parameters include data selected from the group consisting of memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among graphic pipelines, volumes of transferred data, textures count, and depth complexity.

29. The computer system of claim 22, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

30. The computer system of claim 22, wherein the number of said GPU-driven pipeline cores has no architectural limit.

31. The computer system of claim 22, wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

32. The computer system of claim 22, wherein said parallelization modes include an object division mode, an image division mode and a time division mode.

33-45. -45. (canceled)