Semiconductor storage device having a plurality of stacked memory chips

• US 20060233012A1
• Filed: 03/30/2006
• Published: 10/19/2006
• Est. Priority Date: 03/30/2005
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Hitachi, Ltd., Intellectual Property Group Incorporated, Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nagashima, Osamu, Katagiri, Mitsuaki, Sekiguchi, Tomonori, Ido, Tatemi, Osaka, Hideki, Anjo, Ichiro
• Granted Patent: US 7,466,577 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387

Abstract

A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).

Claims

1. A semiconductor storage device comprising:

a base substrate having a command/address external terminal group to which command signals and address signals are supplied, a data input/output external terminal group for inputting and outputting data signals, and a single chip select external terminal; and

a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations, wherein

a plurality of terminals constituting said command/address external terminal group, a plurality of terminals constituting said data input/output external terminal group, and said single chip select external terminal are connected to a single chip that has an interface function; and

the single chip that has the interface function further has at least a chip select signal generation circuit that can individually activate said plurality of memory chips based on said address signals supplied via said command/address external terminal group and based on said chip select signal supplied via said chip select external terminal.

2. The semiconductor storage device as claimed in claim 1, wherein said single chip that has the interface function is an interface chip that is different from said plurality of memory chips.

3. The semiconductor storage device as claimed in claim 1, wherein said single chip that has the interface function is any one chip from among said plurality of memory chips.

4. The semiconductor storage device as claimed in claim 1, wherein at least one of the signals selected from said command signals, said address signals, and said data signals are transmitted between said plurality of memory chips and said single chip that has the interface function by way of wiring with a shared connection to said plurality of memory chips.

5. The semiconductor storage device as claimed in claim 1, wherein at least one of the signals selected from said command signals, said address signals, and said data signals are transmitted between said plurality of memory chips and said single chip that has the interface function by way of wiring that is individually connected to the plurality of memory chips.

6. The semiconductor storage device as claimed in claim 1, wherein said chip select signal generation circuit activates one of said plurality of memory chips based on a portion of said address signals supplied via said command/address external terminal group which is different from a bank address when an activation command is issued.

7. The semiconductor storage device as claimed in claim 6, wherein said chip select signal generation circuit has an active bank register for storing the relationship between the selected bank and the memory chip that is to be activated, and activates one of said plurality of memory chips by referencing said active bank register when a read command or a write command is issued together with said bank address via said command/address external terminal group.

8. The semiconductor storage device as claimed in claim 1, wherein said chip select signal generation circuit sequentially activates said plurality of memory chips when a refresh command is issued.

9. The semiconductor storage device as claimed in claim 1, wherein said single chip that has the interface function further has a clock regeneration circuit, and a clock regenerated by said clock regeneration circuit is supplied to said plurality of memory chips.

10. The semiconductor storage device as claimed in claim 1, wherein said single chip that has the interface function further has a strobe signal generation circuit, and said chip that has the interface function outputs a data signal that is read from said memory chip via said data input/output external terminal group in synchronism with an output of said strobe signal generation circuit.

11. The semiconductor storage device as claimed in claim 1, wherein said single chip that has the interface function has a terminating resistance that is connected to said data input/output external terminal group.

12. The semiconductor storage device as claimed in claim 1, wherein each of said plurality ofmemory chips has a bonding pad area, and said plurality of memory chips are connected to said base substrate by way of tape on which wiring is formed.

13. The semiconductor storage device as claimed in claim 1, wherein a first internal power supply voltage that is lower than an externally supplied high-level-side power supply voltage is applied as a high-level-side power supply voltage, and a second internal power supply voltage that is higher than the externally supplied low-level-side power supply voltage is applied as a low-level-side power supply voltage to an output buffer that is designed to provide output to said plurality of memory chips and is selected from the output buffers included in said single chip that has the interface function.

14. The semiconductor storage device as claimed in claim 1, wherein said plurality of memory chips have a test pad in addition to an ordinary pad designed for actual use, said test pad is connected to a memory array at least via a buffer circuit, and said ordinary pad bypasses said buffer circuit and connects to said memory array.

15. A semiconductor storage device comprising:

a base substrate having a command/address external terminal group to which command signals and address signals are supplied and a single chip select external terminal to which a chip select signal is supplied;

an interface chip that is mounted on the base substrate and is connected to the command/address external terminal group and the chip select external terminal; and

a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations,

wherein said interface chip can individually activate said plurality of memory chips based on said address signals and said chip select signal.

16. The semiconductor storage device as claimed in claim 15, wherein at least one of the signals selected from said command signals and said address signals are transmitted between said plurality of memory chips and said interface chip via wiring with a shared connection to said plurality of memory chips.

17. The semiconductor storage device as claimed in claim 15, wherein at least one of the signals selected from said command signals and said address signals are transmitted between said plurality of memory chips and said interface chip via wiring that is individually connected to the plurality of memory chips.

18. A semiconductor storage device comprising:

a base substrate having a command/address external terminal group to which command signals and address signals are supplied and a single chip select external terminal to which a chip select signal is supplied; and

a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations,

wherein one of said plurality of memory chips is connected to the command/address external terminal group and the chip select external terminal and can individually activate said plurality of memory chips based on said address signals and said chip select signal.

19. The semiconductor storage device as claimed in claim 18, wherein at least one of the signals selected from said command signals and said address signals are transmitted between said one of said plurality of memory chips and a remaining memory chips via wiring with a shared connection to said remaining memory chips.

20. The semiconductor storage device as claimed in claim 18, wherein at least one of the signals selected from said command signals and said address signals are transmitted between said one of said plurality of memory chips and a remaining memory chips via wiring that is individually connected to the remaining memory chips.