Memory device with pre-fetch circuit and pre-fetch method

• US 20060233013A1
• Filed: 04/14/2005
• Published: 10/19/2006
• Est. Priority Date: 04/14/2005
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Tu, Ying Te, Lin, Yu Chang
• Granted Patent: US 7,342,835 B2
• Time in Patent Office: Days
• US Class Current: 365/100
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write data to the selected wordline. A buffer of latches are coupled to the group of first sense amplifiers and have sufficient capacity to hold data corresponding to the selected wordline of memory cells.

Claims

1. A memory device comprising:

a first memory block having memory cells arranged in rows and columns;

a selector coupled to the first memory block to select a row of the memory cells;

a group of amplifiers coupled to the first memory block to at least one of read data from and write data to the selected row; and

a buffer coupled to the group of amplifiers and having sufficient capacity to hold data corresponding to the selected row of memory cells.

2. The memory device of claim 1, wherein the selector is configured to select the row of memory cells only once during at least one of a read operation and a write operation carried out on the selected row.

3. The memory device of claim 1, wherein the buffer comprises a plurality of latches to hold the data corresponding to the selected row of memory cells.

4. The memory device of claim 3, wherein each said latch comprises first and second ports, the first port configured to carry the data associated with a corresponding one of the memory cells and the second port configured to carry a logical inverse of the data carried on the first port.

5. The memory device of claim 4, wherein:

the latch further comprises first and second inverters;

the first port is applied to an input of the first inverter and to an output of the second inverter;

the second port is applied to an output of the first inverter and to an input of the second inverter; and

the output of the first inverter is applied to the input of the second inverter and the first port.

6. The memory device of claim 3, wherein:

the amplifiers are arranged in a first bank of amplifiers and a second bank of amplifiers;

the latches are arranged in a first bank of latches and a second bank of latches;

the first bank of latches are coupled to the first bank of amplifiers;

the first bank of amplifiers are coupled to alternate columns of the memory cells;

the second bank of latches are coupled to the second bank of amplifiers; and

the second bank of amplifiers are coupled to columns of the memory cells between the alternate columns to which the first bank of amplifiers are coupled.

7. The memory device of claim 3, wherein a number of the latches and a number of the amplifiers each corresponds to a number of the columns in the first memory block.

8. The memory device of claim 3, further comprising a second memory block, wherein a portion of the latches are shared between the first memory block and the second memory block.

9. The memory device of claim 8, wherein the selector is a first selector, the memory device further comprising a second selector for selectively activating one of a first and second bank of switches to associate the portion of latches with one of the first and second memory blocks, respectively.

10. A memory device comprising:

a first memory block having memory cells arranged in rows and columns;

a first set of amplifiers coupled to the rows of memory cells in the first memory block to at least one of read data from and write data to the rows of memory cells;

a buffer coupled to the first set of amplifiers to hold data corresponding to one of the rows of memory cells; and

a second set of amplifiers coupled to the buffer to at least one of read data from and write data to the buffer.

11. The memory device of claim 10, wherein the buffer comprises a plurality of latches to hold data corresponding to one of the rows of memory cells.

12. The memory device of claim 11, wherein:

the first set of amplifiers are arranged in a first bank of amplifiers and a second bank of amplifiers;

the latches are arranged in a first bank of latches and a second bank of latches;

the first bank of latches are coupled to the first bank of amplifiers;

the first bank of amplifiers are coupled to alternate columns of the memory cells;

the second bank of latches are coupled to the second bank of amplifiers; and

the second bank of amplifiers are coupled to columns of the memory cells between the alternate columns to which the first bank of amplifiers are coupled.

13. The memory device of claim 11, wherein a number of the latches and a number of the first set of amplifiers each corresponds to a number of columns in the memory block.

14. The memory device of claim 11, further comprising a second memory block, wherein a portion of the latches are shared between the first memory block and the second memory block.

15. The memory device of claim 14, further comprising a selector for selectively activating one of a first and second bank of switches to associate the portion of latches with one of the first and second memory blocks, respectively.

16. A method of reading data from a memory block having rows of memory cells for storing data and an output line, the method comprising:

selecting a first one of the rows of memory cells;

transferring, in a single operation, the data stored in the selected first row of memory cells to a group of latches; and

holding the transferred data in the group of latches.

17. The method of claim 16, further comprising:

de-selecting the first row of memory cells; and

transferring the data held in the group of latches to the output line.

18. The method of claim 17, further comprising:

selecting a second one of the rows of memory cells; and

refreshing the contents of the memory cells in the selected second row of memory cells during the transferring of data held in the latches to the output line.

19. The method of claim 18, wherein the selected second row of memory cells is the first row of memory cells.

20. The method of claim 16, wherein the data stored in the selected first row of memory cells is transferred simultaneously to the group of latches.

21. A method of writing data to a memory block having rows of memory cells for storing data and an input line, the method comprising:

selecting a row of memory cells to receive data;

reading currently held data from the memory cells of the selected row to a group of latches;

transferring data from the input line to at least one latch of the group of latches; and

writing, in a single operation, the data held in the group of latches to the selected row of memory cells.

22. The method of claim 21, further comprising:

de-selecting the row of memory cells.

23. The method of claim 22, wherein the selected row of memory cells is a first row of memory cells, the method further comprising:

selecting a second row of memory cells; and

refreshing the contents of the selected second row of memory cells during the transferring of data from the input line to at least one latch of the group of latches.

24. The method of claim 23, wherein the selected second row of memory cells is the first row of memory cells.

25. The method of claim 21, wherein the data held in the group of latches is transferred simultaneously to the selected first row of memory cells.

26. The method of claim 21, wherein the transferring of data from the input line to at least one latch of the group of latches replaces at least a portion of the data read from the memory cells to the group of latches with the data from the input line.