Non-Volatile Memory with Background Data Latch Caching During Erase Operations

• US 20060233021A1
• Filed: 05/05/2006
• Published: 10/19/2006
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan, Lin, Jason
• Granted Patent: US 7,609,552 B2
• Time in Patent Office: Days
• US Class Current: 365/185.120
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.

Claims

1. A non-volatile memory device having addressable pages of memory cells, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

a state machine for controlling an erase memory operation on a designated group of pages; and

for contemporaneously performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array.

2. The memory device of claim 1, wherein the state machine controls the erase operation to remove charges stored in the memory cells of the designated group of pages.

3. The memory device of claim 1, wherein the state machine controls the erase operation in a first phase, to remove charges stored in the memory cells of the designated group of pages until the memory cells have a threshold voltage below that of a predetermined ground state and

in a second phase to program the memory cells of the designated group of pages substantially to the predetermined ground state.

4. The memory device of claim 3, wherein the second phase further comprises:

said state machine controlling alternately applying a programming pulse to and verifying each of the memory cells of the designated group until each has been programmed to the predetermined ground state.

5. The memory device of claim 1, wherein the memory cells each stores one bit of data.

6. The memory device of claim 1, wherein the memory cells each stores more than one bit of data.

7. The memory device of claim 1, wherein the state machine controls the one or more subsequent memory operations that include one or more program operations.

8. The memory device of claim 7, wherein the memory cells each stores one bit of data.

9. The memory device of claim 8, wherein the state machine controls operations on the set of data latches that include loading a page of binary program data thereto.

10. The memory device of claim 8, wherein the state machine controls operations on the set of data latches that include loading more than one page of binary program data thereto.

11. The memory device of claim 7, wherein the memory cells each stores more than one bit of data.

12. The memory device of claim 11, wherein the state machine controls operations on the set of data latches that include loading a page of binary program data thereto.

13. The memory device of claim 11, wherein the state machine controls operations on the set of data latches that include loading more than one page of binary program data thereto.

14. The memory device of claim 1, wherein the state machine controls the one or more subsequent memory operations that include one or more read operations.

15. The memory device of claim 14, wherein the state machine controls the one or more read operations that are inserted during the second phase.

16. The memory device of claim 14, wherein the state machine controls the one or more read operations that are inserted just prior to the first phase.

17. The memory device of claim 14, wherein the one or more read operations are part of a read scrub operations where existing data stored in the memory cells are read periodically to check for any errors, and when errors are found the corrected data are reprogrammed.

19. The memory device as in any one of claims 14-18, wherein the memory cells each stores one bit of data.

20. The memory device as in any one of claims 14-18, wherein the memory cells each stores more than one bit of data.

18. A non-volatile memory device having addressable pages of memory cells, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

means for controlling an erase memory operation on a designated group of pages; and

means for contemporaneously performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array.