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Non-Volatile Memory with Background Data Latch Caching During Erase Operations

  • US 20060233021A1
  • Filed: 05/05/2006
  • Published: 10/19/2006
  • Est. Priority Date: 04/01/2005
  • Status: Active Grant
First Claim
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1. A non-volatile memory device having addressable pages of memory cells, comprising:

  • a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

    a state machine for controlling an erase memory operation on a designated group of pages; and

    for contemporaneously performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array.

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