Non-Volatile Memory with Background Data Latch Caching During Program Operations
First Claim
1. A non-volatile memory device having addressable pages of memory cells, comprising:
- a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
a control circuitry for controlling a current memory operation on the addressed page, said current memory operation having one or more phases during operation, each phase being associated with a predetermined set of operating states;
a phase-dependent coding provided for each phase so that for at least some of the phases, their set of operating states are coded with substantially a minimum of bits in order to free up a subset of free data latches; and
said control circuitry contemporaneously with the current memory operation, controlling one or more operations on the subset of free data latches with data related to one or more pending memory operations on the memory array.
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Accused Products
Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.
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Citations
18 Claims
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1. A non-volatile memory device having addressable pages of memory cells, comprising:
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a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
a control circuitry for controlling a current memory operation on the addressed page, said current memory operation having one or more phases during operation, each phase being associated with a predetermined set of operating states;
a phase-dependent coding provided for each phase so that for at least some of the phases, their set of operating states are coded with substantially a minimum of bits in order to free up a subset of free data latches; and
said control circuitry contemporaneously with the current memory operation, controlling one or more operations on the subset of free data latches with data related to one or more pending memory operations on the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18)
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15. A non-volatile memory device having addressable pages of memory cells, comprising:
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a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
means for controlling a current memory operation on the addressed page, said current memory operation having one or more phases during operation, each phase being associated with a predetermined set of operating states;
a phase-dependent coding provided for each phase so that for at least some of the phases, their set of operating states are coded with substantially a minimum of bits in order to free up a subset of free data latches; and
means for controlling one or more operations on the subset of free data latches with data related to one or more pending memory operations on the memory array contemporaneously with the current memory operation.
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Specification