Method for Non-Volatile Memory with Background Data Latch Caching During Erase Operations
First Claim
1. A method of operating a non-volatile memory having addressable pages of memory cells, comprising:
- providing for each memory cell of an addressed page a set of data latches having capacity for latching a predetermined number of bits;
performing an erase operation on a designated group of pages; and
contemporaneously with the erase operation, performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array.
3 Assignments
0 Petitions
Accused Products
Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.
-
Citations
19 Claims
-
1. A method of operating a non-volatile memory having addressable pages of memory cells, comprising:
-
providing for each memory cell of an addressed page a set of data latches having capacity for latching a predetermined number of bits;
performing an erase operation on a designated group of pages; and
contemporaneously with the erase operation, performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
Specification