Three-dimensional memory devices and methods of manufacturing and operating the same
First Claim
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1. A memory device comprising:
- a plurality of planes of memory arrays, each memory array including a plurality of memory cells;
a plurality of word lines and bit lines coupled to the memory cells in each plane; and
at least one transistor to select at least one of the memory arrays.
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Abstract
Three-dimensional memory devices and methods of manufacturing and operating the same are disclosed. A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a plurality of word lines and bit lines coupled to the memory cells in each plane, and at least one transistor to select at least one of the memory arrays.
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Citations
17 Claims
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1. A memory device comprising:
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a plurality of planes of memory arrays, each memory array including a plurality of memory cells;
a plurality of word lines and bit lines coupled to the memory cells in each plane; and
at least one transistor to select at least one of the memory arrays. - View Dependent Claims (2, 3, 4, 5)
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6. A method of accessing memory cells, comprising:
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sending a first signal to at least one layer select transistor;
activating the at least one select transistor based on the first signal; and
communicating signals to or from one or more memory cells based on the activated at least one select transistor. - View Dependent Claims (7, 8, 9)
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10. A memory device comprising:
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at least two layers of memory arrays each containing at least four memory cells;
at least two word lines in each layer coupled with the memory cells of the corresponding layer;
at least two bit lines in each layer coupled with the memory cells of the corresponding layer; and
at least a set of layer-selecting transistors for each layer, each set of the layer-selecting transistors being coupled to the memory cells of the corresponding layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification