Video encoding and video/audio/data multiplexing device

• US 20060233261A1
• Filed: 06/14/2006
• Published: 10/19/2006
• Est. Priority Date: 04/06/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yavits, Leonid, Morad, Amir
• Granted Patent: US 9,247,263 B2
• Time in Patent Office: Days
• US Class Current: 375/240.240
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Claims

1-46. -46. (canceled)

47. A multiplexing processor comprising:

a storage unit operable to buffer and transfer video data;

a digital signal processor operable to pipeline said video data from said storage unit;

a memory unit comprising

a first buffer operable to receive the pipelined video data from said storage unit at a first rate, and

a second buffer operable to retrieve the pipelined video data from said first buffer at a second rate, thereby allowing a difference between the first rate and the second rate; and

a video processor operable to retrieve the pipelined video data from said second buffer at the second rate.

48. The multiplexing processor according to claim 47, wherein the storage unit is in external memory.

49. The multiplexing processor according to claim 48, wherein the first rate is an external memory communication rate.

50. The multiplexing processor according to claim 48, wherein said external memory acts as a temporary video buffer, accumulating video data when said digital signal processor is unable to accept said video data.

51. The multiplexing processor according to claim 47, wherein the memory unit is in internal local memory.

52. The multiplexing processor according to claim 51, wherein the second rate is an internal processing rate.

53. The multiplexing processor according to claim 47, wherein the digital signal processor comprises a memory controller operable to control data communication with the video processor.

54. The multiplexing processor according to claim 47, wherein pipelined video data is transferred in a macroblock-by-macroblock manner.

55. A multiplexing processor comprising:

a storage unit operable to buffer and transfer data;

a digital signal processor operable to pipeline said data from said storage unit;

a memory unit comprising

a first buffer operable to receive the pipelined data from said storage unit at a first rate, and

a second buffer operable to retrieve the pipelined data from said first buffer at a second rate, thereby allowing a difference between the first rate and the second rate; and

a co-processor operable to retrieve the pipelined data from said second buffer at the second rate.

56. The multiplexing processor according to claim 55, wherein the storage unit is in external memory.

57. The multiplexing processor according to claim 56, wherein the first rate is an external memory communication rate.

58. The multiplexing processor according to claim 56, wherein said external memory acts as a temporary buffer, accumulating data when said digital signal processor is unable to accept said video data.

59. The multiplexing processor according to claim 55, wherein the memory unit is in internal local memory.

60. The multiplexing processor according to claim 59, wherein the second rate is an internal processing rate.

61. The multiplexing processor according to claim 55, wherein the digital signal processor comprises a memory controller operable to control data communication with the co-processor.