Doping of semiconductor fin devices

• US 20060234431A1
• Filed: 06/05/2006
• Published: 10/19/2006
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Chenming Hu, Fu-Liang Yang, Hao-Yu Chen, Ping-Wei Wang, Yee-Chia Yeo
• Original Assignee: Chenming Hu, Fu-Liang Yang, Hao-Yu Chen, Ping-Wei Wang, Yee-Chia Yeo
• Inventors: Wang, Ping-Wei, Yeo, Yee-Chia, Yang, Fu-Liang, Hu, Chenming, Chen, Hao-Yu
• Granted Patent: US 8,790,970 B2
• Time in Patent Office: Days
• US Class Current: 438/157
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Claims

1. A method of doping semiconductor fins of multiple-gate transistors, the method comprising:

providing a semiconductor structure comprising of a plurality of semiconductor fins overlying an insulator layer, each fin having a gate dielectric overlying a portion of that semiconductor fin, and a gate electrode overlying said gate dielectric, each of the semiconductor fins having a channel region disposed beneath the gate electrode, the channel region located in a top surface, a first sidewall surface, and a second sidewall surface of the semiconductor fin;

implanting dopant ions at an angle α

with respect to the normal of the top surface of each of the semiconductor fins to dope along the first sidewall surface and along the top surface, the angle α

being between 26 degrees and about 63 degrees; and

implanting dopant ions at an angle β

with respect to the normal of the top surface of each of the semiconductor fins to dope along the second sidewall surface and along the top surface, the angle β

being between 26 degrees and about 63 degrees.

2. The method of claim 1 wherein the angle α

has a magnitude that is about equal to the magnitude of angle β

.

3. The method of claim 1 further comprising an annealing process to activate the implanted dopant ions.

4. The method of claim 1 wherein the semiconductor fins are oriented in the same direction.

5. The method of claim 1 wherein each gate electrode has a gate length smaller than 30 nm and each semiconductor fin is oriented in the same direction.

6. The method of claim 1 wherein the semiconductor fins comprise silicon fins.

7. The method of claim 6 wherein the dopant ions are p-type dopant ions selected from the group consisting of boron and indium and combinations thereof.

8. The method of claim 7 wherein the first and second sidewall surfaces are (110) crystallographic surfaces.

9. The method of claim 6 wherein the dopant ions are n-type dopant ions selected from the group consisting of phosphorus, arsenic, and antimony and combinations thereof.

10. The method of claim 9 wherein the first and second sidewall surfaces are (100) crystallographic surfaces.

11. The method of claim 1 wherein each semiconductor fin comprises an etchant mask overlying the semiconductor fin.

12. The method of claim 1 wherein the insulator layer is recessed, resulting in a notch at the base of each of the semiconductor fins.

13. The method of claim 1 wherein the ratio of the doping concentration in a top surface region of the semiconductor fin to the doping concentration in the first sidewall region of the semiconductor fin is between about 1 and about 4.

14. The method of claim 1 wherein the first and second sidewall regions are doped to a doping concentration of more than 1×

10²⁰ cm<sup>−

3</sup>.

15. The method of claim 1 wherein the insulator layer has a thickness of between about 100 angstroms and about 2000 angstroms.

16. The method of claim 1 wherein the gate dielectric layer comprises high permittivity material.

17. The method of claim 16 wherein the high permittivity material is selected from the group consisting of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, and combinations thereof.

18. The method of claim 16 wherein the gate dielectric layer comprises of high permittivity materials with relative permittivity greater than 5.

19. The method of claim 1 wherein the gate electrode comprises poly-crystalline silicon.

20. The method of claim 1 wherein the gate electrode comprises a metal.

21. A method of forming a semiconductor-on-insulator chip, the method comprising:

providing a substrate with an insulator layer formed thereon;

forming a plurality of multiple-gate transistors on the insulator layer, wherein at least some of the multiple-gate transistors are formed by;

forming a semiconductor fin having an orientation in a first direction;

forming a gate electrode formed adjacent a channel region portion of the semiconductor fin, the gate electrode having a gate length of less than about 30 nm;

forming a source region and a drain region within the semiconductor fin such that the channel region is disposed between the source region and the drain region, the channel extending along a first sidewall surface of the fin, across a top surface of the fin and along a second sidewall surface of the fin, wherein the channel region is doped to a first conductivity type and the source and drain regions are doped to a second conductivity type that is different than the first conductivity type, wherein the source and drain regions are doped by implanting ions at an angle between 26 degrees and about 63 degrees with respect to the normal of a top surface of the insulator layer.

22. The method of claim 21 wherein the semiconductor fin is comprised of silicon, and wherein the orientation of the semiconductor fin is in the [110] direction.

23. The method of claim 21 wherein the semiconductor fin is comprised of silicon, and wherein the orientation of the semiconductor fin is in the [100].

24. A method of doping semiconductor fins of multiple-gate transistors, the method comprising:

providing a semiconductor structure comprising of a plurality of semiconductor fins overlying an insulator layer, each fin having a gate dielectric overlying a portion of that semiconductor fin, and a gate electrode overlying said gate dielectric, each of the semiconductor fins having a top surface, a first sidewall surface, and a second sidewall surface;

implanting dopant ions at an angle α

with respect to the normal of the top surface of each of the semiconductor fins to dope a portion of the semiconductor fins, the angle α

having a magnitude between 26 degrees and 63 degrees; and

implanting dopant ions at an angle β

with respect to the normal of the top surface of each of the semiconductor fins to dope a portion of the semiconductor fins, the angle β

having a magnitude between 26 degrees and 63 degrees.

25. The method of claim 24 wherein implanting dopant ions at an angle α

comprises doping the first sidewall surface and the top surface of the semiconductor fins and wherein implanting dopant ions at an angle β

comprises doping the second sidewall surface and the top surface of the semiconductor fins.