METHOD AND STRUCTURE FOR ION IMPLANTATION BY ION SCATTERING

• US 20060234484A1
• Filed: 04/14/2005
• Published: 10/19/2006
• Est. Priority Date: 04/14/2005
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H., Lanzerotti, Louis D., Sheridan, David C.
• Application Number:
  US10/907,752
• Publication Number:
  US 20060234484A1
• Time in Patent Office: Days
• US Class Current: 438/556
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

A scatter-implant process and device is provided where a bi-level doping pattern is achieved in a single doping step. Additionally, devices having different breakdown voltages can be produced in a single implant process. The scatter-implant is fabricated by scattering implant ions off the edge of a mask, thereby reducing the ion energy causing the ions to doping shallower regions than the non-scattered ions which dope a lower region. By adjusting various parameters of the doping process such as, for example, ion type, ion energy, mask type and geometry, in a position of scattering edge relative to other structure of the device, the scatter-implant can be tuned to achieve certain properties of the semiconductor device. Additionally, circuits can be made using the scatter-implant process where pre-selected portion of the circuit incorporate the scatter-implant region and other portions of the circuit do not rely on the scatter region.

Claims

1. A method of adjusting a breakdown voltage of a semiconductor device, comprising the steps of:

providing a scattering edge proximate to a region to be scatter-implanted; and

passing a dose of ions through the scattering edge to scatter a predetermined portion of the dose of ions from the scattering edge into the region to be scatter-implanted to form a semiconductor device having an adjusted breakdown voltage.

2. The method of claim 1, wherein the region to be scatter-implanted comprises an active region of a semiconductor device.

3. The method of claim 1, wherein the region to be scatter-implanted is adjacent an emitter of a semiconductor device.

4. The method of claim 1, further comprising fabricating an electrostatic discharge device comprising the region to be scatter-implanted.

5. The method of claim 4, further comprising fabricating an NPN device comprising the region to be scatter-implanted in the electrostatic discharge device.

6. The method of claim 5, further comprising fabricating a variable trigger comprising the region to be scatter-implanted within the electrostatic discharge device.

7. The method of claim 1, further comprising fabricating at least any one of a semiconductor controlled rectifier, and a multi-finger tunable NPN circuit comprising the region to be scatter-implanted.

8. The method of claim 1, wherein the region to be scatter-implanted is adjacent an emitter of a semiconductor device.

9. The method of claim 1, wherein adjusting a breakdown voltage of a semiconductor device comprises scatter-implanting at least any one of a collector-emitter-base (CEB), collector-base-emitter (CBE), collector-emitter-base-emitter-collector (CEBEC), and collector-base-emitter-base-collector (CBEBC) semiconductor device configuration.

10. A method of forming a bi-level implanted semiconductor device, comprising the steps of:

arranging a scattering edge on a substrate;

forming a lower region of a bi-level implant by directing a first portion of a single dose of ions into a lower layer of the substrate; and

forming an upper region of the bi-level implant by directing a second portion of the single dose of ions into the scattering edge to scatter some ions of the second portion into an upper layer of the substrate.

11. The method of claim 10, wherein an upper region of the bi-level implant is configured to reduce the breakdown voltage of the bi-level implanted semiconductor device.

12. The method of claim 10, further comprising fabricating an electrostatic discharge device clamp comprising the bi-level implant.

13. The method of claim 12, further comprising fabricating an NPN device comprising the bi-level implant within the electrostatic discharge device.

14. The method of claim 13, further comprising fabricating a variable trigger comprising the bi-level implant within the electrostatic discharge device.

15. The method of claim 10, further comprising fabricating at least any one of a semiconductor controlled rectifier, and a multi-finger tunable NPN circuit comprising the bi-level implant.

16. A semiconductor device, comprising:

a substrate having ions of a single dose direct-implanted in the substrate at a lower level and ions of the single dose scatter-implanted in the substrate above the direct-implanted ions to form a scatter-implanted region in the substrate.

17. The semiconductor device of claim 16, wherein the ions scatter-implanted in the substrate above the direct-implanted ions are implanted in an active region of the semiconductor device.

18. The semiconductor device of claim 16, wherein the ions scatter-implanted in the substrate above the direct-implanted ions are implanted adjacent an emitter of the semiconductor device.

19. The semiconductor device of claim 16, comprising at least any one of a collector-emitter-base (CEB), collector-base-emitter (CBE), collector-emitter-base-emitter-collector (CEBEC), and collector-base-emitter-base-collector (CBEBC) semiconductor device configuration.

20. The semiconductor device of claim 16, wherein the semiconductor device comprising the scatter-implanted region is incorporated into an electrical circuit comprising at least any one of an NPN trigger electrostatic discharge (ESD) clamp, semiconductor controlled rectifier (SCR) with variable trigger, scatter circuit ESD, multi-finger tunable NPN circuit, NPN ESD circuit, and variable trigger power clamp.