Method and apparatus to control number of erasures of nonvolatile memory

• US 20060236025A1
• Filed: 04/18/2005
• Published: 10/19/2006
• Est. Priority Date: 04/18/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Eldar, Avigdor
• Application Number:
  US11/107,971
• Publication Number:
  US 20060236025A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Briefly, a method an apparatus and a computational platform to control a number of erasures of a block and/or a sector of nonvolatile memory by allowing a predetermined number of erasures of the sector and/or the block of the nonvolatile memory within a predetermined time interval.

Claims

1. An apparatus comprising:

a controller to control a number of erasures of a nonvolatile memory by allowing a predetermined number of erasures of the nonvolatile memory within a predetermined time interval.

2. The apparatus of claim 1, comprising:

a counter to count a number of erasures of a sector of the nonvolatile memory.

3. The apparatus of claim 1, comprising:

a counter to count a number of erasures of a block of the nonvolatile memory.

4. The apparatus of claim 1, comprising:

a timer to periodically measure the predetermined time interval and wherein the controller is able to vary a number of erasures that where counted by the counter by a predetermined number based on a number of erasures that where counted by the counter during the predetermined time interval.

5. The apparatus of claim 2, wherein the controller is able to reject an attempt to erase the nonvolatile memory based on a count value of the counter.

6. The apparatus of claim 2, wherein the controller is able to set the desirable number of erasures of the nonvolatile memory and the counter is able to count according to the desirable number.

7. The apparatus of claim 1, wherein the nonvolatile memory comprises:

first and second blocks having first and second scratch sectors, respectively, wherein either the first and second scratch sector is randomly selected to be written with data which is addressed to be written on a physical sector of a physical block of the nonvolatile memory

8. A method comprising:

controlling a number of erasures of a nonvolatile memory by allowing a predetermined number of erasures of the nonvolatile memory within a predetermined time interval.

9. The method of claim 8, comprising:

counting the number of erasures of a block of the nonvolatile memory.

10. The method of claim 8, comprising:

counting the number of erasures of a sector of the nonvolatile memory.

11. The method of claim 8, comprising:

periodically varying a number of counted erasures by a predetermined number based on the number of erasures that where counted during a predetermined time interval.

12. The method of claim 8, comprising:

rejecting an attempt to erase the nonvolatile memory based on a desirable number of erasures of the nonvolatile memory.

13. The method of claim 8, comprising:

selecting a sector of a block to store data;

randomly selecting a scratch sector of first and second scratch sector of the nonvolatile memory to be written with the data; and

mapping an address of the scratch sector to reflect an address of the sector.

14. A computational platform comprising:

a management system that include a controller to control a number of erasures of a nonvolatile memory by allowing a predetermined number of erasures of the nonvolatile memory within a predetermined time interval.

15. The computational platform of claim 14, wherein the management system comprises:

a management firmware that includes a counter to count a number of erasures of a sector of the nonvolatile memory.

16. The computational platform of claim 14, wherein the management system comprises:

a management firmware that includes a counter to count a number of erasures of a block of the nonvolatile memory.

17. The computational platform of claim 14, wherein the management system comprises:

a management firmware that includes a timer to periodically measure the predetermined time interval and wherein the controller is able to vary a number of erasures that where counted by the counter by a predetermined number based on a number of erasures that where counted by the counter during the predetermined time interval.

18. The computational platform of claim 15, wherein the controller is able to reject an attempt to erase the nonvolatile memory based on a count value of the counter.

19. The computational platform of claim 15, wherein the controller is able to set to set the desirable number of erasures of the nonvolatile memory and the counter is able to count according to the desirable number.

20. The computational platform of claim 14, wherein the nonvolatile memory comprises:

first and second blocks having first and second scratch sectors, respectively, wherein either the first and second scratch sector is randomly selected to be written with data which is addressed to be written on a physical sector of a physical block of the nonvolatile memory.

21. An article comprising:

a storage medium, having stored thereon instructions, that when executed, result in;

controlling a number of erasures of a nonvolatile memory by allowing a predetermined number of erasures of the nonvolatile memory within a predetermined time interval.

22. The article of claim 21, wherein the instructions when executed result in:

counting the number of erasures of a block of the nonvolatile memory.

23. The article of claim 21, wherein the instructions when executed result in:

counting the number of erasures of a sector of the nonvolatile memory.

24. The article of claim 21, wherein the instructions when executed result in:

periodically varying a number of counted erasures by a predetermined number based on the number of erasures that where counted during a predetermined time interval.

25. The article of claim 21, wherein the instructions when executed result in:

rejecting an attempt to erase the nonvolatile memory based on to an desirable number of erasures of the nonvolatile memory.

26. The article of claim 21, wherein the instructions when executed result in:

selecting a sector of a block to store data;

randomly selecting a scratch sector of first and second scratch sector of the nonvolatile memory to be written with the data; and

mapping an address of the scratch sector to reflect an address of the sector.