System having memory device accessible to multiple processors

• US 20060236041A1
• Filed: 01/31/2006
• Published: 10/19/2006
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sohn, Han-Gu, Kim, Sei-Jin
• Granted Patent: US 8,055,854 B2
• Time in Patent Office: Days
• US Class Current: 711/153
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Claims

1. A system comprising:

a memory device having a first memory array part and a second memory array part;

a first processor predominantly accessing the first memory array part and selectively accessing the second memory array part; and

a second processor predominantly accessing the second memory array part and selectively accessing the first memory array part.

2. The system of claim 1, wherein the memory device further has a third memory array part accessible by the first processor and the second processor.

3. The system of claim 1, further comprising at least one additional memory device connected to at least one of the first memory array part and the second memory array part.

4. The system of claim 1, wherein the first memory array part and the second memory array part are provided with different clock signals.

5. The system of claim 1, wherein the first memory array part and the second memory array part are connected to different power supplies.

6. The system of claim 1, wherein the first memory array part and the second memory array part are connected to different data input/output lines.

7. The system of claim 1, wherein:

the first processor processes first data with a first data width and stores the first data predominantly in the first memory array part and selectively in the second memory array part; and

the second processor processes second data with a second data width and stores the second data predominantly in the second memory array part and selectively in the first memory array part.

8. The system of claim 7, wherein the first data width is different from the second data width.

9. The memory device of claim 8, further comprising a MUX converting the first data width of the first data into the second data width and the second data width of the second data into the first data width.

19. The system of claim 1, wherein the system is a portable communications apparatus.

10. A system comprising:

a baseband processor processing first data with a first data width;

an application processor processing second data with a second data width that is different from the first data width; and

a memory device having a first memory array part and a second memory array part from which data can be read by the baseband processor and the application processor and a MUX converting the first data width of the first data into the second data width and the second data width of the second data into the first data width,

wherein;

the baseband processor writes the first data predominantly to the first memory array part and the application processor writes the second data selectively to the first memory array part; and

the application processor writes the second data predominantly to the second memory array part and the baseband processor writes the first data selectively to the second memory array part.

11. The system of claim 10, wherein the memory device further has a third memory array part commonly accessible by the baseband processor and the application processor.

12. The system of claim 10, wherein the memory device is a dual-port memory device.

13. The system of claim 10, further comprising a mobile DRAM connected to the first memory array part.

14. The system of claim 10, further comprising a mobile DRAM connected to the second memory array part.

15. The system of claim 10, wherein the first memory array part and the second memory array part are provided with different clock signals.

16. The system of claim 10, wherein the first memory array part and the second memory array part are connected to different power supplies.

17. The system of claim 10, wherein the first memory array part and the second memory array part are connected to different data input/output lines.

18. A system comprising:

at least one memory device having a first memory array part and a second memory array part;

at least one first processor associated with the first memory array part; and

at least one second processor associated with the second memory array part,

wherein the at least one first processor is configured to access both the first memory array part and second memory array part.

20. A memory device comprising:

a first memory array part; and

a second memory array part, wherein

the first memory array part is configured to be predominantly accessed by at least one first processor and selectively accessed by at least one second processor and the second memory array part is configured to be predominantly accessed by the at least one second processor and selectively accessed by the at least one first processor.

21. A method of storing data in a system including a first and second processor comprising:

storing data processed by the first processor predominantly in a first memory array part and selectively in a second memory array part; and

storing data processed by the second processor predominantly in the second memory array part and selectively in the first memory array part.