METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM

• US 20060236183A1
• Filed: 06/06/2006
• Published: 10/19/2006
• Est. Priority Date: 02/02/2001
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Granted Patent: US 7,360,127 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. A receive circuit comprising:

a receive data storage element configured to output a receive data output signal based on a receive data input signal received at a receive data input when the receive circuit is operating in a normal mode, the receive data storage element further configured to provide a repeating pattern signal when the receive circuit is operating in a test mode; and

a comparison element configured to perform a comparison of a relationship between the repeating pattern signal and the receive data input signal received at the receive data input and to produce a comparison output signal based on the comparison when the receive circuit is operating in the test mode.

2. The receive circuit of claim 1, wherein the receive data storage element comprises a shift register.

3. The receive circuit of claim 1, further comprising:

a test loop coupled to the receive data storage element when the receive circuit is operating in the test mode, the test loop providing feedback to allow the receive data storage element to provide the repeating pattern signal.

4. The receive circuit of claim 1, wherein the repeating pattern signal has a data length greater than a data capacity of the receive data storage element.

5. The receive circuit of claim 1, wherein the repeating pattern signal represents a sequence of data bits, the receive data storage element storing each of the data bits.

6. The receive circuit of claim 1, wherein, when the receive data storage element is divided into receive data storage sub-elements during operation in the normal mode, the receive data storage sub-elements are combined as the receive data storage element for providing the repeating pattern signal when the receive circuit is operating in the test mode.

7. The receive circuit of claim 1, wherein the receive data storage element is loaded from the receive data input to initialize the test mode.

8. The receive circuit of claim 1, wherein the receive data storage element is loaded from a source other than the receive data input to initialize the test mode.

9. The receive circuit of claim 1, wherein the receive data storage element is loaded via a parallel receive load input

10. The receive circuit of claim 1, wherein the comparison element detects variation of the relationship between the repeating pattern signal and the receive data input signal received at the receive data input.

11. The receive circuit of claim 10, wherein the repeating pattern signal is repeated with a first period and the receive data input signal is repeated with a second period, the first period and the second period bearing a multiple and submultiple relationship to each other.

12. The receive circuit of claim 11, wherein the first period and the second period are equal.

13. The receive circuit of claim 11, wherein the comparison of the relationship between the repeating pattern signal and the receive data input signal is performed over multiple instances of the first period and the second period.

14. The receive circuit of claim 13, wherein the receive circuit communicates the comparison output signal to a source of the receive data input signal.

15. The receive circuit of claim 13, wherein the receive circuit adjusts a parameter affecting its reception of the receive data input signal based on the comparison output signal.

16. The receive circuit of claim 15, wherein the parameter affects reception of a second receive data input signal, the second receive data input signal being distinct from the receive data input signal.

17. A method for improving the operation of a digital signaling system comprising the steps of:

generating a transmit repeating pattern in a transmit circuit;

transmitting the transmit repeating pattern to a receive circuit;

generating a receive repeating pattern in the receive circuit;

comparing the transmitted transmit repeating pattern to the receive repeating pattern in a test mode to obtain a comparison; and

adjusting a parameter affecting reception of the transmit repeating pattern at the receive circuit based at least in part upon the comparison such that the operation of the digital signaling system is improved in a normal mode with the adjusted parameter.

18. A transmit circuit comprising:

a transmit data storage element configured to receive serial data from a transmit data input and sequentially transmit a serial transmit data output signal when the transmit circuit is operating in a normal mode, the transmit data storage element further configured to provide a repeating pattern signal when the transmit circuit is operating in a test mode, the transmit circuit sequentially transmitting the serial transmit data output signal based on the repeating pattern signal when the transmit circuit is operating in the test mode.

19. A receive circuit comprising:

a receive data storage element configured to output a serial receive data output signal based on a serial receive data input signal received at a receive data input when the receive circuit is operating in a normal mode, the receive data storage element further configured to provide a repeating pattern signal when the receive circuit is operating in a test mode; and

a comparison element configured to perform a comparison of a relationship between the repeating pattern signal and the serial receive data input signal received at the receive data input and to produce a comparison output signal based on the comparison when the receive circuit is operating in the test mode.