MEMORY DEVICE WITH SERIAL TRANSMISSION INTERFACE AND ERROR CORRECTION MEHTOD FOR SERIAL TRANSMISSION INTERFACE

• US 20060236204A1
• Filed: 08/24/2005
• Published: 10/19/2006
• Est. Priority Date: 03/17/2005
• Status: Abandoned Application

• Current Assignee: Sunplus Technology Co., Ltd
• Original Assignee: Sunplus Technology Co., Ltd
• Inventors: Lee, Yu-Chu, Huang, Shih-Yu, Chou, Han-Liang
• Application Number:
  US11/161,957
• Publication Number:
  US 20060236204A1
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial transmission interface accesses the memory. Further, the action of error corrections and data re-transmissions performed by the master device can be reduced.

Claims

1. A memory device with a serial transmission interface, comprising:

a serial transmission interface controller, adapted to serially access an external data, and send/receive an internal data in the memory device with the serial transmission interface, the internal data comprising a digital data and a first error correction code;

a memory, coupled to the serial transmission interface controller to store the digital data; and

an error correction code controller, coupled to the serial transmission interface controller and the memory to temporarily store the digital data outputted from the serial transmission interface controller, and to check the digital data according to the first error correction code.

2. The memory device with a serial transmission interface of claim 1, wherein the error correction code controller comprises:

a data buffer, temporarily storing the digital data outputted from the serial transmission interface controller;

a data recovery unit, correcting the digital data accessed by the error correction code controller;

an error correction code decoder, decoding the digital data accessed by the error correction code controller to generate a second error correction code, and comparing the first error correction code and the second error correction code so as to determine the correctness of the digital data;

when the digital data is in error, the data recovery unit is activated to correct the digital data;

when the digital data is in error and the data recovery unit is unable to correct the digital data, the serial transmission interface controller re-accesses the external data; and

a register, temporarily storing the second error correction code so that the error correction code decoder compare the first error correction code and the second error correction code.

3. The memory device with a serial transmission interface of claim 1, wherein the memory comprises an error correction code block to store the first error correction code while the error correction code decoder compares the first error correction code and the second error correction code, and determines the correctness of the digital data.

4. The memory device with a serial transmission interface of claim 3, wherein when the memory device with the serial transmission interface read the digital data, the error correction code block provides the first error correction code stored therein;

the digital data provided by the memory and the first error correction code constitute the internal data, and the internal data is transmitted to the error correction code controller to determine the correctness of the internal data.

5. The memory device with a serial transmission interface of claim 1, wherein the serial transmission interface controller is a serial peripheral interface (SPI) controller.

6. The memory device with a serial transmission interface of claim 1, wherein the memory is a flash memory.

7. An error correction method for a serial transmission interface, adapted for a memory device with a serial transmission interface, the error correction method comprising:

serially accessing and transforming an external data to an internal data of the memory device with the serial transmission interface, wherein the internal data comprises a digital data and a first error correction code; and

checking the digital data by the memory device with the serial transmission interface according to the first error correction code.

8. The error correction method for a serial transmission interface of claim 7, wherein the process of checking the digital data by the memory device with the serial transmission interface according to the first error correction code comprises the following steps:

generating a second error correction code according to the digital data;

comparing the first error correction code and the second error correction code to determine the correctness of the digital data;

correcting the digital data according to the first error correction code when the digital data is in error; and

re-accessing the external data by the memory device with the serial transmission interface when the digital data is in error and a data recovery unit is not able to correct the digital data.