Optical lithography correction process

• US 20060236271A1
• Filed: 04/09/2005
• Published: 10/19/2006
• Est. Priority Date: 04/09/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Invarium, Inc. (Cadence Group)
• Inventors: Zach, Franz Xaver
• Granted Patent: US 7,882,456 B2
• Time in Patent Office: Days
• US Class Current: 716/30
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y10S 977/834 Optical properties of nanomaterial, e.g. specified transparency, opacity, or index of refraction

Abstract

A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.

Claims

1. A pattern enhancement process, comprising the steps of:

characterizing the influence of individual ones of a plurality of worst-case process variations on a simulated nano-circuit layout design; and

correcting said simulated nano-circuit layout design in response to said step of characterizing.

2. The pattern enhancement process according to claim 1, wherein said step of characterizing includes:

establishing said plurality of worst case process variations affecting the performance of a lithographic process; and

applying a base line metric on said simulated nano-circuit layout design.

3. The pattern enhancement process according to claim 2, wherein said step of establishing includes:

defining a first approximation of a lithographic process having a plurality of nominal conditions, wherein each nominal condition is subject to a process variation;

determining a probability distribution for each individual one of said plurality of nominal conditions during a predefined nano-circuit manufacturing process;

predicting said plurality of worst-case process variations affecting the performance of a lithographic process; and

deriving said base line metric in response to said step of predicting.

4. The pattern enhancement process according to claim 2, wherein said step of applying includes:

establishing criteria to identify nano-circuit layout corrections based on said base line metric.

5. The pattern enhancement process according to claim 1, wherein said step of correcting includes:

automatically deriving a repair strategy wherein said repair strategy is based a flagged layout configuration.

6. The pattern enhancement process according to claim 5, wherein said flagged layout configuration is indicative of any deficiency in the group of deficiencies comprising:

a large variation relative to a critical dimension;

an interlevel critical distance violation relative to a spacing distance between a line end and a contact; and

an insufficient gate coverage.

7. The pattern enhancement process according to claim 1, further comprising:

repeating said step of correcting a sufficient number of times to affect an acceptable nano-circuit layout design.

8. The pattern enhancement process according to claim 3, wherein said plurality of nominal conditions includes at least one of the following nominal conditions:

dose;

focus;

aberration;

mask critical dimension;

resist characteristic;

flare;

illumination;

reflectivity.

9. The pattern enhancement process according to claim 2, wherein said step of establishing includes:

defining a set of worst case process conditions;

simulating a post optical proximity correction layout under said set of worst-case process conditions;

evaluating detected errors in said post optical proximity correction layout relative to a target layout; and

creating said base line metric from the detected errors.

10. The pattern enhancement process according to claim 9, wherein said step of creating includes:

a maximum edge movement divided by a next nearest neighbor distance base line metric.

11. The pattern enhancement process according to claim 9, wherein said step of creating includes an edge movement relative to at least one interlevel design rule critical parameter base line metric.

12. The pattern enhancement process according to claim 11, wherein said at least one interlevel design rule critical parameter is a distance to contact parameter.

13. The pattern enhancement process according to claim 9 wherein said base line metric is a desired electrical performance metric derived from a specific structure in said simulated nano-circuit layout design.

14. The pattern enhancement process according to claim 13, wherein said desired electrical performance metric is a resistivity metric of said specific structure.

15. The pattern enhancement process according to claim 13, wherein said desired electrical performance metric is a forward drive current metric of said specific structure.

16. A computer program product for correcting a process critical layout, comprising:

a computer usable medium having computer readable program code means embodied in said medium for causing a process critical layout design implemented in a lithographic process to be corrected, said computer program product having;

computer readable program code means for causing a computer to characterize the influence of individual ones of a plurality of worst case process variations on a simulated nano-circuit layout design to define process criticality in said lithographic process; and

computer readable program code means for causing said computer to automatically locate and correct each individual failure location in said simulated nano-circuit layout design in response to at least one feature on said simulated nano-circuit layout design being flagged as being in need of correction.

17. The computer program product according to claim 16, wherein said computer readable program code means for causing a computer to characterize includes:

computer readable code means for causing said computer to establish a methodology for determining a plurality of worst case process variations affecting the performance of said lithographic process; and

computer readable code means for causing said computer to apply a base line metric on said simulated nano-circuit layout design.

18. The computer program product according to claim 17, wherein said computer readable code means for causing said computer to establish includes:

computer readable code means for causing said computer to define a first approximation of a lithographic process having a plurality of nominal conditions, wherein each nominal condition is subject to a process variation;

computer readable code means for causing said computer to determine a probability distribution for each individual one of said plurality of nominal conditions during a predefined nano-circuit manufacturing process;

computer readable code means for causing said computer to predict whether any individual one of said plurality of worst case process variations will detrimentally influence the performance of said lithographic process during said predefined nano-circuit manufacturing process; and

computer readable code means for causing said computer to derive said base line metric in response to said computer predicting whether any individual one of said plurality of worst case process variations will detrimentally influence the performance of said lithographic process during said predefined nano-circuit manufacturing process.

19. An apparatus for correcting a process critical layout, comprising:

an optical rules correction processor which implements the steps of;

evaluating a detected error in a predicted wafer image relative to a target wafer image;

creating a metric for process criticality based on a predicted edge movement and a resulting deviation in an electrical performance characteristic derived from said detected error;

selecting at least one layout geometry based on said metric to determine whether said at least one layout geometry requires modification to improve it electrical performance characteristic; and

automatically performing at least one modification to said at least one geometry layout when it requires modification to improve its electrical performance characteristic.

20. The apparatus for correcting a process critical layout according to claim 19, wherein said step of evaluating includes:

defining in a semiconductor manufacturing process a plurality of process parameters essential to the production of a desired nano-circuit layout, said nano-circuit layout having a plurality of features;

determining a worst case value for each individual one of said plurality of process parameters during said semiconductor manufacturing process;

simulating said desired nano-circuit layout to characterize each individual one of said plurality of features in said desired nano-circuit layout relative to said worst case value for each individual one of said plurality of process parameters; and

wherein said step of selecting is any one of the following;

a threshold algorithm to said metric;

moving a design edge away from its critical dimensions;

adding a resolution enhancement feature.