Semiconductor flash device

• US 20060237770A1
• Filed: 04/20/2005
• Published: 10/26/2006
• Est. Priority Date: 04/20/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Fu-Liang, Huang, Chien-Chao, Min-Hwa, Chi
• Granted Patent: US 7,602,006 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.

Claims

1. A floating gate transistor comprising:

a lower tunnel-oxide formed over a substrate;

an upper dielectric formed over said tunnel-oxide;

a control gate formed over said upper dielectric; and

a p-n junction formed between said tunnel-oxide and said upper dielectric.

2. The floating gate transistor as in claim 1, wherein said p-n junction comprises a quantum well.

3. The floating gate transistor as in claim 1, wherein said p-n junction is a heterojunction formed between two layers of semiconductor material having different bandgaps.

4. The floating gate transistor as in claim 3, wherein said different bandgaps differ by at least 0.05 ev.

5. The floating gate transistor as in claim 3, wherein said two layers comprise a layer of SiGe and a layer of Si.

6. The floating gate transistor as in claim 3, wherein said two layers comprise a first layer formed of III-V material and a second layer formed of II-VI material.

7. The floating gate transistor as in claim 1, wherein said p-n junction is a heterojunction formed between a layer of n-Si and a layer of p-SiGe and said p-n junction comprises an electron quantum well.

8. The floating gate transistor as in claim 7, wherein said Si comprises p-Si and said SiGe comprises n-SiGe and said p-n junction comprises an hole quantum well.

9. The floating gate transistor as in claim 1, further comprising a further p-n junction and wherein said p-n junction and said further p-n junction are created by three layers formed between said tunnel-oxide and said upper dielectric, said three layers including a middle semiconductor layer with a first bandgap interposed between an upper semiconductor layer and a lower semiconductor layer each formed of a material having a different bandgap than said middle semiconductor layer.

10. The floating gate transistor as in claim 1, wherein said lower tunnel-oxide includes a thickness of less than 90 angstroms and said upper dielectric includes a thickness of less than 90 angstroms.

11. The floating gate transistor as in claim 1, further comprising a semiconductor fin disposed on said substrate and wherein said lower tunnel-oxide extends along said substrate and conterminously over said semiconductor fin and a channel of said transistor is formed within said semiconductor fin.

12. The floating gate transistor as in claim 1, wherein said floating gate transistor is erasable using a voltage no greater than 8 volts.

13. The floating gate transistor as in claim 1, wherein said floating gate transistor is programmable using a voltage no greater than 8 volts.

14. The floating gate transistor as in claim 1, wherein said floating gate transistor is an NMOS transistor and mobile carriers stored at said p-n junction comprise electrons.

15. The floating gate transistor as in claim 1, wherein said floating gate transistor is an NMOS transistor and mobile carriers stored at said p-n junction comprise holes.

16. The floating gate transistor as in claim 1, wherein said floating gate transistor comprises a PMOS transistor.

17. A semiconductor flash memory device comprising:

a lower tunnel-oxide formed over a substrate;

an upper dielectric formed over said tunnel-oxide;

a control gate formed over said upper dielectric;

a quantum well formed at a p-n junction disposed between said tunnel-oxide and said upper dielectric; and

charge stored in said quantum well.

18. The semiconductor flash memory device as in claim 17, wherein said p-n junction is a heterojunction formed between two layers of semiconductor material, said two layers comprising an n-type layer adjacent a p-type layer and including respective bandgaps that differ by at least 0.05 eV.

19. The semiconductor flash memory device as in claim 17, further comprising a semiconductor fin disposed on said substrate and wherein said lower tunnel-oxide extends along said substrate and conterminously over said semiconductor fin, wherein a channel of said transistor is formed within said semiconductor fin.

20. A floating gate transistor comprising:

a lower tunnel-oxide formed over a substrate;

an upper dielectric formed over said tunnel-oxide;

an electrode formed over said upper dielectric; and

a quantum well formed between said tunnel-oxide and said upper dielectric.