Hybrid carbon nanotube FET(CNFET)-FET static RAM (SRAM) and method of making same

• US 20060237857A1
• Filed: 01/13/2006
• Published: 10/26/2006
• Est. Priority Date: 01/14/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Rueckes, Thomas, Guo, Frank, Meinhold, Mitchell, Konsek, Steven L.
• Granted Patent: US 7,598,544 B2
• Time in Patent Office: Days
• US Class Current: 257/427
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/17 Memory cell being a nanowire transistor
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Claims

1. A static ram memory cell, comprising:

two semiconductor-type field effect transistors (FETs), each FET having a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions, said channel region made of a second type of semiconductor material, each FET further having a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate, wherein the two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other; and

two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, connected to a respective source and drain region of a corresponding NTFET, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

2. The SRAM cell of claim 1, wherein the two semiconductor-type FETs are formed in a substrate, and the two NTFETs are positioned above the two semiconductor-type FETs.

3. The SRAM cell of claim 2 wherein the NTFETs are vertically aligned with a corresponding semiconductor-type FET.

4. The SRAM cell of claim 1 wherein the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of p-type nanotubes.

5. The SRAM cell of claim 1 wherein the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of ambipolar-type nanotubes.

6. The SRAM cell of claim 1 wherein NTFETs also include a back control gate.

7. An intermediate SRAM structure comprising:

an organized and structured arrangement of SRAM cells, each SRAM cell having

two semiconductor-type field effect transistors (FETs), each FET having a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions, said channel region made of a second type of semiconductor material, each FET further having a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate, wherein the two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other; and

two nanotube FETs (NTFETs), each having a channel region made of nanotubes including nanotubes of semiconductive and metallic type, connected to a respective source and drain region of a corresponding NTFET, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET;

burn-off circuitry to electrically stimulate the channel regions of the NTFETs to fail nanotubes of metallic type while leaving at least one nanotube of semiconductor type.

8. The intermediate SRAM cell of claim 7 wherein SRAM cell select transistors are used as burn-off select transistors.

9. The intermediate SRAM cell of claim 8 wherein select transistors are controlled by dedicated burn-off circuitry.

10. The intermediate SRAM cell of claim 9 wherein burn-off control circuits are operational prior to completion of chip wiring.

11. The intermediate SRAM cell of claim 10 wherein burn-off control circuits are operational prior to formation of SRAM functional circuits.

12. A method of electrically connecting two conductive or semiconductive entities vertically displaced relative to each other, comprising:

forming a void to create a pathway between the two entities, wherein an upper opening of the void is in proximity to the first entity and a bottom of the void abuts the second entity;

depositing a conformal fabric of nanotubes to adhere to a top surface next to the upper opening of the void to contact the first entity, and to adhere conformally to the vertical surface of the void, and to adhere to the bottom surface of the void to contact the second entity.