RFID system including a memory for correcting a fail cell and method for correcting a fail cell using the same

• US 20060238310A1
• Filed: 12/12/2005
• Published: 10/26/2006
• Est. Priority Date: 04/21/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok, Ahn, Jin Hong
• Granted Patent: US 7,313,037 B2
• Time in Patent Office: Days
• US Class Current: 340/10.510
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a failed cell correcting circuit in a memory. In the RFID system, a predetermined number of unit cells are separated into one memory group, and the same data are stored in each memory group at a write mode. At a read mode, the cell data of the selected memory group are compared, and the same data are identified as effective data to improve yield of the RFID system.

Claims

1. A radio frequency identification (RFID) system, comprising:

an analog block adapted and configured to transmit data to an external communication apparatus and receive data from said external communication apparatus;

a digital block adapted and configured to receive a power voltage and a signal for data transmission from the analog block, and to transmit a response signal to the analog block; and

a memory adapted and configured to store the same data in each memory group consisting of a predetermined number of unit cells at a write mode, and to compare cell data of said each memory group selected at a read mode to identify the same data as effective data.

2. The RFID system according to claim 1, wherein the memory comprises:

a plurality of memory cell arrays each including the predetermined number of unit cells connected serially; and

a correction unit adapted and configured to compare cell data in said each memory group and to identify the same data as effective data.

3. The RFID system according to claim 2, wherein each of the plurality of memory cell arrays further comprises:

a first switch adapted and configured to selectively connect the predetermined number of unit cells to a plurality of bit lines arranged in a column direction in response to a first selecting signal; and

a second switch adapted and configured to selectively connect the predetermined number of unit cells to a sensing line in response to a second selecting signal.

4. The RFID system according to claim 3, wherein the unit cell comprises:

a first gate connected to a word line;

a second gate connected to a bottom word line;

a ferroelectric layer adapted and configured to store data or output the stored data depending on voltages applied to the first gate and the second gate; and

a float channel layer in which channel is formed depending on a polarity of the ferroelectric layer.

5. The RFID system according to claim 2, wherein the correction unit comprises:

a plurality of sense amplifiers adapted and configured to amplify data of the unit cell;

a plurality of column switches adapted and configured to selectively transmit data amplified in the plurality of sense amplifiers in response to a column selecting signal; and

a comparison unit adapted and configured to identify whether the data amplified in the plurality of sense amplifiers is identical to output the compared data.

6. The RFID system according to claim 5, further comprising a column decoder adapted and configured to generate a plurality of the column selecting signals for controlling the column switch configured to selectively transmit data amplified in the sense amplifier corresponding to said each memory group in response to a column address.

7. The RFID system according to claim 5, wherein the comparison unit comprises:

a comparison unit adapted and configured to identify whether data amplified in the sense amplifier corresponding to said each memory group is identical; and

a plurality of data output switch units adapted and configured to selectively transmit the identical data in response to an output signal from the comparison unit.

8. The RFID system according to claim 7, wherein the comparison unit further comprises a plurality of data input switch units adapted and configured to selectively transmit externally inputted data in response to a write enable signal.

9. The RFID system according to claim 7, wherein each of the plurality of comparison units comprises an exclusive OR gate.

10. The RFID system according to claim 7, wherein each of the plurality of data output switch comprises a plurality of transistors adapted and configured to have a control terminal for receiving an output signal from the plurality of comparison units and to selectively transmit data amplified in the sense amplifier.

11. The RFID system according to claim 2, wherein the unit cell comprises:

a first switch unit and a second switch unit each adapted and configured to have a control terminal connected to a word line and to selectively transmit cell data to a pair of bit lines, respectively; and

a first ferroelectric capacitor and a second ferroelectric capacitor each adapted and configured to have one terminal connected to a plate line and the other terminal connected to the first switch unit and the second switch unit, respectively.

12. The RFID system according to claim 11, wherein the correction unit comprises:

a plurality of sense amplifiers adapted and configured to amplify data of the unit cell;

a plurality of column switches adapted and configured to selectively transmit data amplified in each of the plurality of sense amplifiers in response to the column selecting signal; and

a comparison unit adapted and configured to identify whether the data amplified in each of the plurality of sense amplifiers are identical and to output the identical data.

13. The RFID system according to claim 12, further comprising a column decoder adapted and configured to generate a plurality of the column selecting signals for controlling the column switch configured to selectively transmit data amplified in the sense amplifier corresponding to the memory group in response to a column address.

14. The RFID system according to claim 12, wherein the comparison unit comprises:

a comparison unit adapted and configured to identify whether data amplified in each of the plurality of sense amplifiers corresponding to each of the memory groups are identical; and

a plurality of data output switch units adapted and configured to selectively transmit the identical data in response to an output signal from the comparison unit.

15. The RFID system according to claim 14, wherein the comparison unit further comprises a plurality of data input switch units adapted and configured to selectively transmit externally inputted data in response to a write enable signal.

16. The RFID system according to claim 14, wherein each of the plurality of comparison units comprises an exclusive OR gate.

17. The RFID system according to claim 14, wherein each of the data output switch comprises a plurality of transistors adapted and configured to have a control terminal for receiving an output signal from each of the plurality of comparison units and to selectively transmit data amplified in each of the plurality of sense amplifiers.

20. The method according to claim 1, wherein each of the predetermined number of unit cells is a double gate cell.

18. A method for correcting a failed cell of a RFID system, which the RFID system comprises an analog block adapted and configured to transmit data to an external communication apparatus and receive data from said external communication apparatus;

a digital block adapted and configured to receive a power voltage and a signal for data transmission from the analog block, and to transmit a response signal to the analog block; and

a memory adapted and configured to receive the memory control signals and to correct the failed cell, the method comprising;

a writing step of writing the same data in a memory group including a predetermined number of unit cells; and

a comparing step of comparing data stored in the memory group to identify the same data as effective data.

19. The method according to claim 18, wherein the comparing step comprises:

sensing and amplifying the written data in the selected memory group;

comparing the amplified data; and

identifying the same data as effective data depending on the comparison result.