Apparatus and methods to share time and frequency data between a host processor and a satellite positioning system receiver

• US 20060238415A1
• Filed: 04/22/2005
• Published: 10/26/2006
• Est. Priority Date: 04/22/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gilkes, Alan Martin
• Granted Patent: US 7,545,316 B2
• Time in Patent Office: Days
• US Class Current: 342/357.640
• CPC Class Codes: G01S 19/235 Calibration of receiver components
• CPC Class Codes: G01S 19/256 relating to timing, e.g. time of week, code phase, timing offset

Abstract

Methods and apparatus to share time and frequency data between a host processor and a satellite position system (SPS) receiver in a satellite positioning system are disclosed. An example method disclosed herein generates a host processor local time based on a real-time clock associated with the host processor; adjusts the host processor local time to synchronize with a SPS time received from the SPS receiver and to correct a local frequency error of the real-time clock of the host processor; calculates an estimated SPS time based on the adjusted real-time clock signal of the host processor; and attempts to fix a SPS time and a position of the SPS receiver from SPS signals received from a plurality of SPS satellites based on the estimated SPS time.

Claims

1. A host processor in communication with a SPS receiver comprising:

a real-time clock;

a time computing device to estimate a SPS time based on the real-time clock; and

a conversion factor adjuster to adjust the time computing device to synchronize a time developed from the real-time clock with a SPS time received from the SPS receiver and to correct a local frequency error of the real-time clock.

2. A host processor as defined in claim 1 wherein the host processor outputs the estimated SPS time to support a SPS receiver location and SPS time fix attempt by the SPS receiver.

3. A host processor as defined in claim 2 wherein the host processor further comprises a transmitter to transmit an electronic pulse at substantially the estimated SPS time followed by a message containing a first value representative of the estimated SPS time.

4. A SPS receiver in communication with a host processor comprising:

a receiver to receive an estimated SPS time based on a real-time clock signal of the host processor; and

a radio processor to receive SPS signals from a plurality of satellites, wherein the radio processor attempts to derive a SPS time and SPS receiver location from SPS signals received from a plurality of SPS satellites and the estimated SPS time.

5. A SPS receiver as defined in claim 4 wherein the SPS receiver further comprises a time recorder to record:

(a) a first value representative of a local time of the SPS receiver substantially simultaneous to the estimated SPS time;

(b) a second value representative of a SPS time value derived from the received SPS time signals; and

(c) a third value representative of a second local time of the SPS receiver substantially simultaneous to the derived SPS time.

6. A SPS receiver as defined in claim 5 wherein the second local time of the SPS receiver is substantially the time when an electronic pulse from the host processor is received.

7. An SPS receiver as defined in claim 5 wherein the SPS receiver outputs the first, second, and third representative values to facilitate estimation of SPS times by the host processor.

8. An SPS receiver as defined in claim 5 wherein the SPS receiver calculates a local clock calibration factor and outputs the local clock calibration factor to facilitate estimation of SPS times by the host processor.

9. A SPS receiver in communication with a host processor comprising

a radio processor to receive SPS signals from a plurality of satellites, wherein the radio processor attempts to derive a SPS time and SPS receiver location from SPS signals received from a plurality of SPS satellites;

and

wherein the SPS receiver outputs the derived SPS time to facilitate estimation of SPS times by the host processor.

10. A SPS receiver as defined in claim 9 wherein the SPS receiver further comprises a time recorder to record:

(a) a first value representative of a first local time of the SPS receiver;

(b) a second value representative of a SPS time value derived from the received SPS time signals; and

(c) a third value representative of a second local time of the SPS receiver substantially simultaneous to the derived SPS time.

11. A SPS receiver as defined in claim 10 wherein the first local time of the SPS receiver is substantially the time when transmitting an electronic pulse to the host processor.

12. An SPS receiver as defined in claim 10 wherein the SPS receiver outputs the first, second, and third representative values to facilitate estimation of SPS times by the host processor.

13. An SPS receiver as defined in claim 10 wherein the SPS receiver calculates a local clock calibration factor and outputs the local clock calibration factor to facilitate estimation of SPS times by the host processor.

14. A method of sharing time and frequency data between a host processor and a SPS receiver comprising:

developing a local time of the host processor based on a real-time clock associated with the host processor;

deriving a SPS time and SPS receiver location from SPS signals received from a plurality of SPS satellites; and

using the derived SPS time to adjust parameters associated with developing the local time of the host processor based on the real-time clock to correct a local frequency error of the real-time clock.

15. A method as defined in claim 14 further comprising:

calculating an estimate of SPS time based on the local time of the host processor developed from the real-time clock associated with the host processor; and

wherein deriving the SPS time and the SPS receiver location from the SPS signals received from the plurality of SPS satellites uses the estimated SPS time.

16. A method as defined in claim 15 wherein calculating the estimate of SPS time based on the local time of the host processor developed from the real-time clock associated with the host processor comprises using a programmable scale factor;

and

wherein using the derived SPS time to adjust the parameters associated with developing the local time of the host processor based on the real-time clock to correct the local frequency error of the real-time clock comprises updating the programmable scale factor based upon a first difference between the estimated SPS time and a first local time of the SPS receiver and a second difference between a second local time of the SPS receiver and the derived SPS time.

17. A method as defined in claim 15 further comprising:

developing a second local time from a second real-time clock;

computing a first difference between the estimate of SPS time and the second local time; and

computing a second difference between the derived SPS time and a third local time developed from the second local clock;

wherein adjusting parameters associated with developing the local time of the host processor based on the real-time clock to correct a local frequency error of the real-time clock uses the first and second differences.

18. A method as defined in claim 17 wherein computing the first difference between the estimate of SPS time and the second local time comprises computing a difference between the estimate of SPS time and the second local time developed from the second local clock substantially simultaneous to the estimated SPS time;

and

wherein computing the second difference between the derived SPS time and the third local time developed from the second local clock comprises computing a difference between the derived SPS time value and the third local time developed from the second local clock substantially simultaneous to the derived SPS time.

19. A method as defined in claim 17 wherein the first real-time clock is associated with the host processor and the second real-time clock is associated with the SPS receiver.

20. A method as defined in claim 15 wherein the host processor and the SPS receiver are located in a single housing.

21. A method as defined in claim 14 wherein developing the local time based on the real-time clock associated with the host processor comprises using a programmable scale factor;

and

wherein using the derived SPS time to adjust the parameters associated with developing the first local time of the host processor based on the real-time clock to correct the local frequency error of the real-time clock comprises updating the programmable scale factor based upon a first difference between a local time of the host processor and a first local time of the SPS receiver and a second difference between a second local time of the SPS receiver and the derived SPS time.

22. A method as defined in claim 14 further comprising:

developing a second local time from a second real-time clock;

computing a first difference between a local time of the host processor and the second local time; and

computing a second difference between the derived SPS time and a third local time developed from the second local clock;

wherein adjusting parameters associated with developing the local time of the host processor based on the real-time clock to correct the local frequency error of the real-time clock uses the first and second differences.

23. A method as defined in claim 22 wherein computing the first difference between a local time of the host processor and the second local time comprises computing a difference between a local time of the host processor that is substantially simultaneous to the second local time;

and

wherein computing the second difference between the derived SPS time and the third local time developed from the second local clock comprises computing a difference between the derived SPS time value and the third local time developed from the second local clock substantially simultaneous to the derived SPS time.

24. A method as defined in claim 22 wherein the first real-time clock is associated with the host processor and the second real-time clock is associated with the SPS receiver.

25. A method as defined in claim 14 wherein the host processor and the SPS receiver are located in a single housing.