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NAND Flash Memory Device Having Dummy Memory cells and Methods of Operating Same

  • US 20060239077A1
  • Filed: 04/13/2006
  • Published: 10/26/2006
  • Est. Priority Date: 04/20/2005
  • Status: Active Grant
First Claim
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1. A NAND flash memory device comprising:

  • a plurality of memory cells connected in series;

    at least one dummy memory cell connected in series with the plurality of memory cells;

    a selection transistor connected in series with the dummy memory cell and the plurality of memory cells; and

    a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of the memory cells, a second word line voltage greater than the first word line voltage to a selected memory cell, and a third word line voltage lower than the first word line voltage to the dummy memory cell.

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