NAND Flash Memory Device Having Dummy Memory cells and Methods of Operating Same

• US 20060239077A1
• Filed: 04/13/2006
• Published: 10/26/2006
• Est. Priority Date: 04/20/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal, Shin, Yoo-Cheol, Sel, Jong-Sun, Park, Ki-Tae
• Granted Patent: US 7,480,178 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

Claims

1. A NAND flash memory device comprising:

a plurality of memory cells connected in series;

at least one dummy memory cell connected in series with the plurality of memory cells;

a selection transistor connected in series with the dummy memory cell and the plurality of memory cells; and

a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of the memory cells, a second word line voltage greater than the first word line voltage to a selected memory cell, and a third word line voltage lower than the first word line voltage to the dummy memory cell.

2. The NAND flash memory device of claim 1, wherein the selected memory cell is a program inhibit cell.

3. The NAND flash memory device of claim 2, wherein the selection transistor is connected between the dummy memory cell and a bit line, and the control circuit is configured to apply a power supply voltage to the bit line.

4. The NAND flash memory device of claim 2, wherein the selection transistor is connected between the dummy memory cell and a common source line.

5. A NAND flash memory device comprising:

a plurality of memory cells connected in series;

at least one dummy memory cell connected in series with the plurality of memory cells;

a selection transistor connected in series with the dummy memory cell; and

a control circuit configured to program the dummy memory cell before and/or after erase operations on the plurality of memory cells and the dummy memory cell.

6. The NAND flash memory device of claim 5, wherein the control circuit is configured to perform an erase verification operation after an erase operation on the plurality of memory cells and the dummy memory cell.

7. The NAND flash memory device of claim 6, wherein a control circuit is configured to apply, during the erase verification operation, a first erase verify voltage to the memory cells, and a second erase verify voltage greater than the first verify voltage to the dummy memory cell.

8. The NAND flash memory device of claim 7, wherein the first erase verify voltage is 0V.

9. The NAND flash memory device of claim 7, wherein the second erase verify voltage is sufficient to turn on the dummy memory cell while performing an erase verification operation.

10. A NAND flash memory device comprising:

a plurality of memory cells connected in series;

at least one dummy memory cell connected in series with the plurality of memory cells;

a selection transistor connected in series with the dummy memory cell; and

a control circuit configured not to erase the dummy memory cell while erasing the plurality of memory cells.

11. The NAND flash memory device of claim 10, wherein the control circuit is configured to float a word line of the dummy memory cell while erasing the plurality of memory cells.

12. The NAND flash memory device of claim 10, wherein the control circuit is configured to perform an erase verification operation after an erase operation on the plurality of memory cells and the dummy memory cell.

13. The NAND flash memory device of claim 12, wherein the control circuit is configured to apply, during the erase verification operation, a first erase verify voltage to the memory cells, and a second erase verify voltage greater than the first verify voltage to the dummy memory cell.

14. The NAND flash memory device of claim 13, wherein the first erase verify voltage is 0V.

15. The NAND flash memory device of claim 13, wherein the second erase verify voltage is sufficient to turn on the dummy memory cell while performing an erase verification operation.

16. A NAND flash memory device comprising:

a plurality of memory cells connected in series;

at least one dummy memory cell connected in series with the plurality of memory cells;

a selection transistor connected in series with the dummy memory cell; and

a control circuit configured to apply, during the erase verification operation, a first erase verify voltage to the memory cells, and a second erase verify voltage greater than the first verify voltage to the dummy memory cell.

17. The NAND flash memory device of claim 16, wherein the first erase verify voltage is 0V.

18. The NAND flash memory device of claim 16, wherein the second erase verify voltage is sufficient to turn on the dummy memory cell while performing an erase verification operation.