Method for Non-Volatile Memory with Managed Execution of Cached Data

• US 20060239080A1
• Filed: 05/05/2006
• Published: 10/26/2006
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan
• Granted Patent: US 7,463,521 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.

Claims

1. A method of operating a non-volatile memory having addressable pages of memory cells, comprising:

providing for each memory cell of an addressed page a set of data latches having capacity for latching a predetermined number of bits;

providing a first-in-first-out queue for ordering incoming memory operations to be executed in the core array, the first-out memory operation being the next memory operation to be executed;

specifying a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined;

accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation; and

whenever an executing memory operation in the core array is mergeable with one or more queued memory operations, terminating the executing memory operation and instead executing the combined memory operation of the mergeable memory operations;

or whenever two or more queued memory operations are mergeable among themselves but not with an executing memory operation in the core array, executing the combined queued memory operation of the mergeable memory operations after the executing memory operation in the core array has completed.

2. The method of claim 1, wherein the incoming memory operation is a program operation.

3. The method of claim 1, wherein the data associated with the program operation is a page of binary program data to be programmed.

4. The method of claim 1, wherein the memory cells individually store binary data.

5. The method of claim 2, wherein the memory cells individually store binary data.

6. The method of claim 3, wherein the memory cells individually store binary data.

7. The method of claim 1, wherein the memory cells individually store multi-bits of data.

8. The method of claim 2, wherein the memory cells individually store multi-bits of data.

9. The method of claim 3, wherein the memory cells individually store multi-bits of data.

10. The method of claim 9, wherein each of the multi-bits of data in the page of memory cells forms a single bit of data of a corresponding logical page such that there are as many logical pages as there are multi-bits for each page of memory cells.

11. The method of claim 10, wherein the incoming operation is one of a plurality of program operations each for programming a logical page of data.

12. The method of claim 11, wherein the set of mergeable conditions includes when the data associated with the memory operations to be merged are from logical pages belonging to the same page of memory cells.

13. The method of claim 12, wherein the set of mergeable conditions includes when the memory operations to be merged are queued in a predetermined order.

14. The method of claim 13, wherein the predetermined order is specified by a coding system for the multi-bits memory cell.

15. The method of any one of claims 7-14, wherein the memory cells each stores two bits of data.

16. The method of any one of claims 7-14, wherein the memory cells each stores more than two bits of data.

17. The method of claim 14, wherein:

the coding system is for a 2-bit memory cell having a lower bit and an upper bit; and

the predetermined order is from the lower bit to the upper bit.

18. The method of claim 17, wherein:

the memory operations to be merged include a program operation on a lower-bit page and a program operation on an upper-bit page.

19. The method of claim 14, wherein:

the coding system is for a 3-bit memory cell having a lower bit, a middle bit and an upper bit; and

the predetermined order is from the lower bit to the middle bit to the upper bit.

20. The method of claim 19, wherein:

the memory operations to be merged include a program operation on a lower-bit page and a program operation on a middle-bit page.

21. The method of claim 19, wherein:

the memory operations to be merged include a program operation on a middle-bit page and a program operation on an upper-bit page.

22. The method of claim 19, wherein:

the memory operations to be merged include a program operation on a lower-bit page, a program operation on a middle-bit page and a program operation on an upper-bit page.