NAND flash memory with read and verification threshold uniformity

• US 20060239081A1
• Filed: 05/01/2006
• Published: 10/26/2006
• Est. Priority Date: 05/08/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,274,600 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. The first word line signal voltage level is adjusted in response to the position of the first accessed cell in its series of cells.

Claims

1. A non-volatile memory device comprising:

a memory array comprising a plurality of memory cells arranged in columns and rows, each column coupled to a bit line and each row coupled to a word line, each column coupled to array ground; and

controller circuitry, coupled to the memory array, for controlling operation of the device, the controller circuitry adapted to execute a method for increasing read and erase verification threshold uniformity comprising adjusting a selected word line signal voltage level, coupled to a first accessed cell, in response to a position of the first accessed cell with respect to array ground.

2. The device of claim 1 wherein the controller circuitry generates a second word line voltage to a second accessed cell such that the second word line voltage is greater than the first word line voltage when the second accessed cell'"'"'s position is further from array ground than the first accessed cell.

3. The device of claim 1 wherein the controller circuitry generates a second word line voltage to a second accessed cell such that the second word line voltage is less than the first word line voltage when the second accessed cell is closer to array ground than the first accessed cell.

4. The device of claim 1 wherein the non-volatile memory device is comprised of a NAND flash architecture.

5. The device of claim 1 wherein the controller circuitry determines the position of the first accessed cell by decoding an address input to the non-volatile memory device.

6. The device of claim 1 wherein the control circuitry adjusts the first word line voltage by:

decoding an input address to generate the first word line signal having a nominal voltage level; and

compensating the nominal voltage level in response to the position of the first accessed cell.

7. The device of claim 6 wherein the control circuitry compensates the nominal voltage level by coupling the first word line signal having the nominal voltage level to a resistor divider voltage generator circuit.

8. The device of claim 6 wherein the control circuitry compensates the nominal voltage level by coupling the first word line signal having the nominal voltage level to an analog to digital converter acting as a voltage generator circuit.

9. A NAND flash memory device comprising:

a memory array comprising a plurality of memory cells coupled in rows and columns, a first end of each column coupled to a bit line and a second end of each column coupled to array ground; and

control circuitry, coupled to the memory array, the control circuitry adapted to execute methods for controlling operation of the memory device including determining a position, with reference to the array ground, of a first accessed cell of the plurality of memory cells, generating a word line signal having a first voltage level in response to an address input, and compensating the first voltage level in response to the position of the first accessed cell.

10. The device of claim 9 wherein the control circuitry compensates the first voltage level by increasing the first voltage level in response to the position of the first accessed cell being further from the array ground.

11. The device of claim 9 wherein the control circuitry compensates the first voltage level by adjusting the first voltage level towards a nominal voltage level in response to the position of the first accessed cell being closer to the array ground.

12. An electronic system comprising:

a processor that generates memory signals; and

a flash memory device, coupled to the processor, that operates in response to the memory signals, the device comprising;

a memory array comprising a plurality of memory cells arranged in rows and columns, a first end of each column coupled to a bit line and a second end coupled to array ground potential;

a column decoder that generates the bit line;

a row decoder that generates each word line signal having a nominal voltage level; and

a voltage generator circuit, coupled between the row decoder and the memory array, for adjusting the nominal voltage level in response to a position of a first memory cell in a column as indicated by the word line.

13. The system of claim 12 wherein the voltage generator circuit is a voltage divider network.

14. The system of claim 12 wherein the voltage generator circuit is an analog-to-digital converter that uses a plurality of word lines generated by the row decoder to adjust the nominal voltage level.

15. A NAND flash memory device comprising:

a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference; and

control circuitry, coupled to the memory array, the control circuitry adapted to execute a method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising reading a first cell of the plurality of cells, determining a position of the first cell with reference to a ground potential in the flash memory device, and generating a reference current in response to the position.

16. The device of claim 15 wherein the control circuitry is further adapted to compare a measured current from the first cell with the reference current and determine a value of the read first cell in response to the comparison.

17. A NAND flash memory device comprising:

a memory array comprising a plurality of memory cells coupled in a row and column configuration, a first end of each column coupled to a bit line and a second end coupled to array ground; and

control circuitry, coupled to the memory array, the control circuitry adapted to execute a method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising reading a first cell of the plurality of cells, determining a position of the first cell with reference to array ground, and generating one of a reference current or voltage in response to the position.

18. The device of claim 17 wherein the control circuitry is further adapted to compare a measured voltage from the first cell with the reference current or voltage and determine a value of the read first cell in response to the comparison.

19. An electronic system comprising:

a controller circuit that generates memory signals; and

a non-volatile memory device, coupled to the controller circuit, that operates in response to the memory signals, the device comprising;

a memory array comprising a plurality of cells coupled together in a plurality of columns; and

a reference generator that generates a reference indicator for each of the plurality of cells based on their locations in each of the plurality of columns.

20. The system of claim 19 wherein the reference generator comprises a plurality of memory locations that store a table indicating a reference current for each of the plurality of cells.